Random number generation

[ttrostel]

I have a chunk of code I found on the internet which uses a metastable circuit to generate true random numbers (attached).

When I go to try to create a bitstream for this design it complains that I have a combinatorial loop (intentional) and that I need to change the error into a warning if thats what I really want.  I haven't figured out how to do that exactly in Vivido.  I'm guessing it can't go in the constraint file ... or maybe there is a screen somewhere that you can pick the design rule checks you want to use or not?

Anyhow here's the code ... it's a Galois Ring Oscilator (GARO)

module GARO (input stop,clk, reset, output random);

(* OPTIMIZE="OFF" *)                    //stop *xilinx* tools optimizing this away
wire [31:1] stage /* synthesis keep */; //stop *altera* tools optimizing this away
reg meta1, meta2;

assign random = meta2;

always@(posedge clk or negedge reset)
if(!reset)
  begin
    meta1 <= 1'b0;
    meta2 <= 1'b0;
  end
else if(clk)
  begin
    meta1 <= stage[1];
    meta2 <= meta1;
  end

assign stage[1] = ~&{stage[2] ^ stage[1],stop};
assign stage[2] = !stage[3];
assign stage[3] = !stage[4] ^ stage[1];
assign stage[4] = !stage[5] ^ stage[1];
assign stage[5] = !stage[6] ^ stage[1];
assign stage[6] = !stage[7] ^ stage[1];
assign stage[7] = !stage[8];
assign stage[8] = !stage[9] ^ stage[1];
assign stage[9] = !stage[10] ^ stage[1];
assign stage[10] = !stage[11];
assign stage[11] = !stage[12];
assign stage[12] = !stage[13] ^ stage[1];
assign stage[13] = !stage[14];
assign stage[14] = !stage[15] ^ stage[1];
assign stage[15] = !stage[16] ^ stage[1];
assign stage[16] = !stage[17] ^ stage[1];
assign stage[17] = !stage[18];
assign stage[18] = !stage[19];
assign stage[19] = !stage[20] ^ stage[1];
assign stage[20] = !stage[21] ^ stage[1];
assign stage[21] = !stage[22];
assign stage[22] = !stage[23];
assign stage[23] = !stage[24];
assign stage[24] = !stage[25];
assign stage[25] = !stage[26];
assign stage[26] = !stage[27] ^ stage[1];
assign stage[27] = !stage[28];
assign stage[28] = !stage[29];
assign stage[29] = !stage[30];
assign stage[30] = !stage[31];
assign stage[31] = !stage[1];

endmodule

 

[jpeyron]

Hi ttrostel,

I used the command in the error message set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]  and added it to the constraints file. Generated the bitstream and got the same error again but Vivado added another constraint file that i copied the same command  set_property SEVERITY {Warning} [get_drc_checks LUTLP-1] into and re-generated the bitstream with success! I included my project below.

cheers,

Jon

Random_Number_esc.zip

[ttrostel]

Your project doesn't work for me ... its giving me the same error as before ... there must be some magic somewhere :-)

 

... And it does .... 

If you pick project settings and then pick bitstream at the top it lets you specify a pre.tcl file which will be run before generation.  I created a file called pre.tcl with that one line in it.  Then set the file name with the ellipsis to the right.

THAT actually works.  Putting it in a constraint file doesn't get picked up.

[jpeyron]

Hi ttrostrel,

I am using Vivado 2016.2 with the arty board. What set up are you using?  I used this to help me figure out what to do.  I re-did the project but this time just added  set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]  to the constraint file initially and i was able to generate a bitstream without any issue. 

thank you,

Jon

Rando_Arty_esc.zip

GARO.v

Arty_Master.xdc

[Alex]

Is it necessary for you to have true random number? Otherwise, you can use the pseudo random number. Here is an example: http://www.instructables.com/id/Sequence-Detector-Using-Digilent-Basys-3-FPGA-Boar/?ALLSTEPS It may be totally for reference.