How to boot Microblaze from flash on a board without DDR memory

[jaberroteran10]

Is anyone here being able to boot a microblaze app from flash from a board with no DDR memory like CMOD S7?

Also using Vivado/Vitis 2023.1. 

I have tried to follow the examples/tutorials online but they all used older version of the tools and I havent being able to do this.

Wondering if anyone can offer some suggestions

Thanks in advance

Jose Berroteran 

[artvvb]

Hi @jaberroteran10,

Welcome to the forums!

I ran through this guide with a Cmod A7-35T today and it worked fine in Vivado/Vitis 2023.1 for me: https://www.instructables.com/Flashing-a-MicroBlaze-Program/.

A couple of notes:

1. It's easy to miss the bitstream configuration settings, like setting master SPI x4 mode, so please be sure to pay close attention to those steps.

2. A "Tristate CCLK pin during configuration" setting has been added to the Edit Device Properties -> Configuration screen. I left this as default.

3. The ELF file can be found in the application project binaries folder in Vitis after build:

4. I built the software app for Debug configuration, which could make a difference, and haven't tested building for Release.

Thanks,

Arthur

[jaberroteran10]

Hi @artvvb

Thanks for replying. Few questions before i try your suggestion. 

Right now I have access to a Arty S7 board. For my design I plan to use a Spartan 7 FPGA as well but no external memory since the SW application i am trying to redesign is small ( <128 KB). From my understanding, I should be able to just run my microblaze app with the FPGA's block RAM. 

First, with the Arty S7 board. Can i just follow these directions to create my block design: 
https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi

and use these instructions:
 > Add a Microblaze Processor to a Block Design
 > Follow the steps in this dropdown for boards without DDR memory

Do I need to add the QSPI Flash IP to my block design? I've tried tutorials where they added this IP but I am thinking is not necessary unless I want to have access to it after configuration. (I plan to write the Flash controller in the FPGA and just add a custom IP to my block design).

 

 This step (See below) of the https://www.instructables.com/Flashing-a-MicroBlaze-Program/ is a bit confusing. After I create the gpio demo application and generate the gpio_demo.elf file. I return to Vivado and add the gpio_demo.elf file as a "Design Source" or "Constraint Source". Other tutorials just added it as a design source which makes sense not a constraint file.  

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Step 3: Adding the ELF to the Vivado Project

Return to Vivado and add a new constraint to the project. Locate the .ELF file generated by the SDK. The file will be located in PROJECT_ROOT/PROJECT_NAME.sdk/SDK_PROJECT_NAME/Debug/ where:

PROJECT_ROOT is the folder where your Vivado project file is stored

PROJECT_NAME is the name of your vivado project

SDK_PROJECT_NAME is the name that you gave your SDK project

Click OK until you return to the main Vivado window.

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The other steps are pretty straightforward. 

Is there a need for a SREC bootloader file? Other tutorials use it to store the uP application in the flash

 

Again thanks for replying I am trying to understand this process for when I need it with my upcoming design. 

[jaberroteran10]

Hi @artvvb

 

It worked on my Arty S7.

 

Thanks for your help

 

 

[artvvb]

On 1/5/2024 at 5:45 PM, jaberroteran10 said:

 

Is there a need for a SREC bootloader file? Other tutorials use it to store the uP application in the flash

No SREC bootloader required. They're typically used to copy a larger application from flash into DDR and then jump to start running the copied application. In that scenario, the bootloader would be merged with the bitstream similar to how the ELF file is merged here (though I believe Vitis/SDK will do that part under the hood, not positive) so that it starts running as soon as the bitstream is programmed into the FPGA. Whatever program runs on startup has to fit in Microblaze local memory, which an SREC bootloader can, but those larger apps running out of DDR cannot. Hope this helps.