Hi @artvvb
Thanks for replying. Few questions before i try your suggestion.
Right now I have access to a Arty S7 board. For my design I plan to use a Spartan 7 FPGA as well but no external memory since the SW application i am trying to redesign is small ( <128 KB). From my understanding, I should be able to just run my microblaze app with the FPGA's block RAM.
First, with the Arty S7 board. Can i just follow these directions to create my block design:
https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi
and use these instructions:
> Add a Microblaze Processor to a Block Design
> Follow the steps in this dropdown for boards without DDR memory
Do I need to add the QSPI Flash IP to my block design? I've tried tutorials where they added this IP but I am thinking is not necessary unless I want to have access to it after configuration. (I plan to write the Flash controller in the FPGA and just add a custom IP to my block design).
This step (See below) of the https://www.instructables.com/Flashing-a-MicroBlaze-Program/ is a bit confusing. After I create the gpio demo application and generate the gpio_demo.elf file. I return to Vivado and add the gpio_demo.elf file as a "Design Source" or "Constraint Source". Other tutorials just added it as a design source which makes sense not a constraint file.
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Step 3: Adding the ELF to the Vivado Project
Return to Vivado and add a new constraint to the project. Locate the .ELF file generated by the SDK. The file will be located in PROJECT_ROOT/PROJECT_NAME.sdk/SDK_PROJECT_NAME/Debug/ where:
PROJECT_ROOT is the folder where your Vivado project file is stored
PROJECT_NAME is the name of your vivado project
SDK_PROJECT_NAME is the name that you gave your SDK project
Click OK until you return to the main Vivado window.
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The other steps are pretty straightforward.
Is there a need for a SREC bootloader file? Other tutorials use it to store the uP application in the flash
Again thanks for replying I am trying to understand this process for when I need it with my upcoming design.