dpti Genesys2 DPTI

[odoong]

Hello everyone,

We are trying to use DPTI of genesys2 to send and receive data from PC.

This is the waveform of ftdi signals that are captured by ILA.

As you can see, "ftdi_clk" does not work and it is tied up to 1.

How can we activate the FTDI clock?

[zygot]

I have a project for the Genesys2 that uses the DPTI here: https://forum.digilent.com/topic/25315-using-ddr-as-a-video-frame-buffer/

Don't forget to install the ADEPT2 runtime and SDK.

What are you clocking your ILA with? Doesn't seem that much is happening....

[odoong]

Thank you, zygot.

At the beginning, we connected the ftdi_clk to ILA as its clock.

However, because the ftdi_clk did not work, we used 100MHz clock from system clock of genesys2 as ILA's clock.

[zygot]

It should be apparent that if you clock the ILA with ftdti_clk, then you can't use use it as an ILA data signal. Also, keep clocks and logic signals in their own lane, so to speak; don't use logic signals as clocks and don't use clocks as logic signals.

Any design that uses the Genesys2 sysclk or a clock derived from sysclk, and uses ftdi_clk, has at least two clock domains in the design. Using signals from one clock domain in a different clock domain is a bad idea. There are ways to create copies of a signal in one clock domain that are usable in another clock domain. That's the proper way to go. When you create an ILA that is clocked by a 100 MHz clock that is derived from the Genesys2 200 MHz sysclk, and then sample signals in a different clock domain, you are forcing the tools to violate proper clock domain crossing techniques. At best this will cause timing closure problems. Most likely it will result in an unstable design.

Here's a simple technique that I use to make sure that clocks that I think are there really are. Create a n-bit free-running counter that just wraps around from max count to zero. Send one of the higher count bits to an LED. If you choose correctly, you should be able to see the LED blink at roughly 1 Hz.

[zygot]

Digilent has the ADEPT runtime and SDK, but also provides AXI based DPTI IP that is separate from the ADEPT code examples. I haven't used the sources from Digilent's vivado-library-master repository.

According to FTDI's documentation, it's not possible to use synchronous 245 FIFO mode unless the FTDI chips is configured from the EEPROM to work in 245 FIFO mode and the D2XX driver is selected. The FTDI clock output is only enabled when in 245 FIFO mode. That's what FTDI says. Digilent's documentation seems to contradict this by claiming that you can use either synchronous 245 FIFO mode or asynchronous 245 mode without changing the EEPROM contents. Either they know something that FTDI won't share with the rest of us or there's a mystery here. Anyone can view the default FTDI EEPROM contents for their Digient board. I don't recommend that anyone try and modify this unless they know what they are doing as you can cause big problems.