Arty-Z7 boards and XUartLite Interrupts

[bloggins666]

I've been working for a few weeks now to get interrupts working on my board. I've defined the XUartlite device and got it working under polling mode both in bare metal and using FreeRTOS. However when I try to implement the device under interrupts I find no joy.

I stepped back and tried a simpler approach and using FreeRTOS I got the 4 GPIO based push buttons to work under interrupts. So armed now with that knowledge I felt that the XUartLite device should be an easy transition. Since then I've actually had 1 birthday but I feel like I've had 10. There is no joy to be had using XUartLite under interrupts. I've trolled many of the forums and have found no one that has any actual examples of working code or a "Eureka" moment as far as I can see. I have actually found people saying that it will never work since the tools are broken when it comes to this part of the device.

Has anyone on any of the Xilinx 7000 devices gotten the XUartLite implementation to work with interrupts either bare metal or FreeRTOS?

 

Cheers!!

[artvvb]

Hey @bloggins666

So the baseline issue is that the XUartLite examples aren't built to target Zynq chips, seeing as the PS UART controllers could be used instead. Given that, there are a couple options:

First, EMIOs could be used to connect the spare PS UART controller to PL pins. This is likely the "more correct" approach in a vacuum since it uses fewer FPGA resources. It would entail editing the Zynq PS configuration in Vivado to enable the second PS UART, make its UART interface on the PS block external, and constrain the IOs. Care should be taken to use the right device IDs when loading the XUartPs examples as you would also have another PS UART enabled, which is used for standard input/output.

Second, the XUartLite interrupt example could be adapted to use XScuGic instead of XIntc (the latter is the driver for the AXI interrupt controller commonly used with Microblaze systems). The below is a modified version of SetupInterruptSystem from xuartlite_intr_example, which is based on code from the xuartps interrupt example. It worked in a cursory test in hardware on another board for me, though I didn't scope the TX->RX loopback to check if signals were actually going out of the board. The only other change to the file needed was to replace the xintc.h inclusion with xscugic.h. The Get/SetPriorityTriggerType calls were recommended by this thread: https://support.xilinx.com/s/question/0D52E00006iI3urSAC/uartlite-interrupts-not-working-on-zynq.

Quote

int SetupInterruptSystem(XUartLite *UartLitePtr)
{
    int Status;

    XScuGic_Config *CfgPtr = XScuGic_LookupConfig(XPAR_SCUGIC_SINGLE_DEVICE_ID);
    Status = XScuGic_CfgInitialize(&InterruptController, CfgPtr, CfgPtr->CpuBaseAddress);
    if (Status != XST_SUCCESS) {
        return XST_FAILURE;
    }

    Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
             (Xil_ExceptionHandler)XScuGic_InterruptHandler,
             &InterruptController);

    Status = XScuGic_Connect(&InterruptController, XPAR_FABRIC_AXI_UARTLITE_0_INTERRUPT_INTR,
               (XInterruptHandler)XUartLite_InterruptHandler,
               (void *)UartLitePtr);
    if (Status != XST_SUCCESS) {
        return XST_FAILURE;
    }

    // Set trigger to rising edge sensitive
    u8 Priority, Trigger;
    XScuGic_GetPriorityTriggerType(&InterruptController, 
            XPAR_FABRIC_AXI_UARTLITE_0_INTERRUPT_INTR, &Priority, &Trigger);
    XScuGic_SetPriorityTriggerType(&InterruptController, 
            XPAR_FABRIC_AXI_UARTLITE_0_INTERRUPT_INTR, Priority, 0b11);

    XScuGic_Enable(&InterruptController, XPAR_FABRIC_AXI_UARTLITE_0_INTERRUPT_INTR);

    Xil_ExceptionEnable();

    return XST_SUCCESS;
}

Edit: In case it matters, this is baremetal in Vivado/Vitis 2023.1.

Hope this helps,

Arthur