bloggins666

I've been working for a few weeks now to get interrupts working on my board. I've defined the XUartlite device and got it working under polling mode both in bare metal and using FreeRTOS. However when I try to implement the device under interrupts I find no joy. I stepped back and tried a simpler approach and using FreeRTOS I got the 4 GPIO based push buttons to work under interrupts. So armed now with that knowledge I felt that the XUartLite device should be an easy transition. Since then I've actually had 1 birthday but I feel like I've had 10. There is no joy to be had using XUartLite under interrupts. I've trolled many of the forums and have found no one that has any actual examples of working code or a "Eureka" moment as far as I can see. I have actually found people saying that it will never work since the tools are broken when it comes to this part of the device. Has anyone on any of the Xilinx 7000 devices gotten the XUartLite implementation to work with interrupts either bare metal or FreeRTOS? Cheers!!

Thanks for your reply and I've amended my code accordingly. Now I have dead address space (as I write to the GPIO registers the s/w goes off into the weeds so I need to track that down), but I am making (slow) progress. I did post a question to Ms. Knitter about the lack of FreeRTOS support in the latest Vitis tool. I use the "classic" parameter so that I get the older Vitis SDK. I'm partial to the eclipse based IDE's and I despise the M$oft Vs Code based IDE's. Personal opinion, not trolling. Cheers!!

I've just working with my Arty Z7 20 board and am trying to bring it up with a FreeRTOS image with a console that I wrote so that I can exercise the various devices (LED's, switches, I2C, SPI etc...) that are on the board. I've used Vivado to create a bitstream that has axi_gpio_0, axi_gpio_1, axiuartlite_0 all connected and I've generated the bitstream file and have been able to get started working on the s/w project in Vitis. BTW, I'm using all 2023.2 versions of the Xilinx tools. I had the uart working just fine at first so I am confident that the bitstream is correct. (I did some changes and blew up the project files). I've created a new project from Vivado to just exercise the LED's and a push button that are connected to axi_gpio_0. It's been a dismal failure. I have a series of questions that will I hope, lead me to understanding the tools a bit better with this topic to help me see what "version" of s/w and level (I speak of PS vs PL and the X designations in the imported code). When I speak of "version" here I am using the Xilinx tools 2023.2 but when I generate the s/w using Vitis (I'm using classic, there is an issue with the new Vitis and FreeRTOS on the digilent Arty Z7 board, it doesn't appear to be supported). So when I create my s/w I have a look at the imported project code under: /design_1_wrapper/ps7_cortexa9_0/freertos10_xilinx_ps7_cortexa9_0/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/ There is also: /design_1_wrapper/ps7_cortexa9_0/freertos10_xilinx_ps7_cortexa9_0/bsp/ps7_cortexa9_0/libsrc/gpio_v4_10 So I'm looking at the gpiops_v3_12 and gpio_v4_10 which is confusing me. Is one the Processing System which is referred to as PS and the one with labelled "gpio_v4_10" the PL layer? Which should I be using? When I go looking for example code for turning on and off LED's I find code examples that use both types and I'm not sure what I should be doing to proceed here. Any guidance would be greatly appreciated. Even a reference to some literature that will set me straight about this would be of great help. Cheers!!

Thanks Arthur, I've watched Whitney's videos and found them very good (although I don't like her cat's attitude, it's as if it doesn't care!). I'll check around and see if I can put the process together from bits and pieces of both of them. Thanks for all you help!! And now it's Pub time. Cheers!!

Thanks Artvvb, I have sent both files to AMD/Xilinx support along with a write-up and as I mentioned, no response as of yet. It's been about 10 days. Since I want a more up to date and complete FreeRTOS system I'll probably stick with the bare metal project and then just write in the OS as an application. My next task is to get the petalinux image to work. I've not even come close to getting that up and running. Are there any tutorials on that for this board? I see in the Digilent page "out of the box" images that are for using the HDMI but nothing on just getting petalinux up and running on this board. Cheers!!

This is great guys and I thank you for finding this information. So another issue... When I created a Vivado project for the Arty-Z7(20) board I launched the Vitis tool (classic) I created a FreeRTOS project. I made sure it built and then used the "migrate" option from within the Vitis -classic tool that is provided so I can then run the Vitis IDE 2023 tool to migrate the older project format to the newer. It fails. It will work with a bare metal project but not with FreeRTOS added in (I say added in since in fact FreeRTOS is a bare metal application with some nice juicy bits added on). I captured the error output from two different scenarios. One from the migrate attempt and is attached as vitis-migrate-error.txt I then tried to create a FreeRTOS based project within Vitis IDE and it failed. I've attached the output as vitis-freertos-error.txt I've posted these issues on the Xilinx support site as well and some people have looked at it but there have been no responses and I wonder if it's because this is not their board? I have a small issue with the Vitis SDK version of FreeRTOS as it appears to be older and does not include some of the Add-ons so I may see how to import the version of FreeRTOS that I want into the image. Be prepared for the kind of Whining and Complaining that only a fat 63 yr old is capable of. lol.. Cheers!! "To err is human but, to forgive is NOT corporate policy" vitis-migrate-error.txt vitis-freertos-error.txt

I'm a bit vague (I'm definitely a novice with FPGA tools, 30+ years as an embedded developer though) as to how the XSA file is used or generated. I was able to work through the bare metal tutorial to generate the XSA file from Vivado and then import it to a Vitis environment and then generate the image and load it. All worked fine. I now want to create a linux image for my board (it's Digilent's Arty-Z7 20, but that is actually immaterial). I would imagine I want an XSA file that not only describes the ARM processor and the LEDS (from the tutorial) but in fact has the IP for all of the devices, GPIO's etc... for the entire board. Am I correct in assuming that is not in the XSA file I generated for the tutorial? I had to actually create the instances of the ports and buttons for the LED's and buttons. I would think that the work do define all of the interfaces and whatever is a much more involved process. My essential question is, where do I get this XSA file or am I making a wrong assumption here? Thanks for any answers or advice in advance. Cheers!!

I have discovered that if you launch the Vitis IDE mentioned (the older one appears to be referred to as the Vitis SDK) from the command line (linux) you can pass the parameter "--classic" and you will get the eclipse based framework. This might get you through the tutorial. I haven't steeled myself to start over just yet. Explain to me again how FPGA's were going to make our lives easier? Lol... Cheers!!

Greetings, I was able to successfully install the Linux implementation of the Xilinx tools Vivado & Vitis (2023.2). I'm working with a Digilent Arty Z7 board. I'm following the 2nd tutorial "Getting Started with Vivado and Vitis for Baremetal Software Projects" from the Digilent product page: here I was able to follow the tutorial quite well for the Vivado setup, no errors and then it was time to use the Vitis section. I'm on this page: here However, the Vitis tool has obviously changed from an eclipse based framework to what looks like something similar to Visual Studio. Does a tutorial to use this new framework exist? Perhaps one of the other boards has a tutorial for this new version? Cheers!!