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Learn Module 5 for FPGAs question


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I've been working on learning how to use FPGAs on my own and was feeling pretty good after finding a nice getting started guide for Vivado and some introductory projects using Verilog and successfully getting those projects to work on the Arty and even using some external IO with the Pmod ports since the Arty doesn't have all of the embedded switches and what not that some of the other Digilent boards seem to have. I'm using Vivado 2015.3 with the WebPack edition (maybe the Design Edition, I don't know if my voucher ran out yet or not).

But my question is on the project 5 in the 4-bit shifter portion at the bottom (for both the ISE version and the Vivado version since it seems to be verilog based so it shouldn't really matter which one I use). I was feeling pretty brave and tried to do the project myself without looking at the provided code but kept getting a combinatorial loop error when I got to the bitstream generation portion, so I tried out the code that was provided in the project, but much to my surprise I received a combinatorial loop error too! Problem is, I don't really know what that means or how I might change the code so that it's less combining since it does a variety of inputs to make the shifter work...

Basically, I'm at a loss as how to approach fixing this problem. I tried changing the sensitivity list in the always block (I think that's the right term) to just executing when I press the enable button (since that's the only time I'd want the shift to happen anyway), including all of the changing variables that Vivado suggested in the warnings created during synthesis, as well as just the variable used in the Project 5. 

I was really looking forward to trying out the other projects that are available but I figure I probably shouldn't try them until I get past the basics first.

I'm not sure what all people might want to look at so I attached my verilog file, the XDC I modified from the "master" Arty xdc, and the error I'm getting.

Here's the error: 
[DRC 23-20] Rule violation (LUTLP-1) Combinatorial Loop - 5 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. To allow bitstream creation for designs with combinatorial logic loops (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. led_OBUF[1]_inst_i_1, led_OBUF[1]_inst_i_2, led_OBUF[2]_inst_i_1, led_OBUF[3]_inst_i_2, led_OBUF[3]_inst_i_3.

the top module: top.v

and the xdc: Arty_Master.xdc

Any advice on how to resolve this would be great.



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Hi Natsu,

I got you code to generate a bitstream. top.v   You will need to fix the if and else statements where led_wire = 3'b000; and led_wire = 3'b111;

 if(Rotate == 0)
            led_wire = 3'b000; 
            //(Direction == 0) ? {Fill,led[3:1]} : {led[2:0],Fill};
            led_wire = 3'b111;
            //(Direction == 1) ? {led[2:0],led[3]} : {led[0],led[3:1]};


 I did not change anything with the xdc file.



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  • 2 months later...

Hi Jon,

I obviously haven't been back on here for awhile, but I did finally get that code working (after months of not looking at it). The problem I ended up having was I was having the LED output be based on the current LED state rather than the current switch state...XD. Since this nicely creates a recursive function (did I mention recursion?) or combinatorial loop in FPGA land, Vivado nicely decided to avoid letting me do that. Of course, the learn module based the outputs (leds) on the inputs (switches) and did not run into this problem...evidently I didn't actually read through example code to see that was the case. Next time I'll try to make sure that I actually read the answer before saying that it's wrong.

Thanks for helping me out.


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