Using the ARTY_A7 onboard flash for user data storage.

[Dante]

I am currently using the Digilent Arty A7-100T development board. I would like to use the onboard flash (S25FL128SAG) to store user data. From the schematic I can see the CLK pin of the flash is connected to the configuration clock of the FPGA (CCLK_0) and it is not addressable through the constraint file. 
 

• Is it possible to control or access the CCLK_0 pin after the FPGA configuration phase for SPI communication?
• If direct control of CCLK_0 is not feasible, what alternative methods can I use to communicate with the SPI flash?
• Has anyone dealt with a similar situation and can offer insights or share their approach?

 

Best,
Dante. 

[artvvb]

Hi Dante,

Apologies for the delay.

QSPI_SCK is also connected to pin L16. Access to CCLK_0 could also be achieved using the STARTUPE2 primitive.

https://digilent.com/reference/programmable-logic/arty-a7/reference-manual#quad-spi_flash

We'll need to look into why a location constraint for L16 is missing from the template XDC file. I would expect the following to work:

Quote

set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { qspi_sck }];

Thanks,

Arthur

[Dante]

Still seeking assistance: I've turned my attention to interfacing with an off-board flash due to challenges in my initial approach. If anyone has insights or alternative suggestions, please share. Your expertise would be greatly appreciated!

[Dante]

Thank you @artvvb, with your advice I was able to successfully interface with the onboard flash.