The resulting HW design is published in the repository together with a simple memory read speed test app (I wrote the critical benchmarking code in assembly).
In a hobby project of mine (I ported ILI9488 TFT display library to Xilinx SoC and FPGA), I needed to create a test HW design for MicroBlaze. I couldn't find a tutorial which I would like.
Therefore, I created one after considerable research and testing. I hope it helps other people in their learning curve.
Any feedback on the tutorial and resulting HW design is welcome. 🙂
Please note that in this HW design, I, on purpose, deviated from some parts of Arty A7 DDR3 documentation and from this tutorial.
The difference is that I'm using an external 100 MHz clock for the MIG input System Clock instead of the 166.67 MHz recommended in Arty A7 documentation. Using an internally generated clock for MIG System Clock is strongly not recommended by Xilinx documentation (I received this feedback on the Xilinx support forum).
I explain this topic in more detail here.
Edited by Viktor Nikolov Added info about Vivado 2024.1
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Viktor Nikolov
I would like to share that I created a detailed step-by-step tutorial for making an HW design of MicroBlaze using DDR3 on the Arty A7 board (in Vivado 2023.1 or Vivado 2024.1).
The resulting HW design is published in the repository together with a simple memory read speed test app (I wrote the critical benchmarking code in assembly).
In a hobby project of mine (I ported ILI9488 TFT display library to Xilinx SoC and FPGA), I needed to create a test HW design for MicroBlaze. I couldn't find a tutorial which I would like.
Therefore, I created one after considerable research and testing. I hope it helps other people in their learning curve.
Any feedback on the tutorial and resulting HW design is welcome. 🙂
Please note that in this HW design, I, on purpose, deviated from some parts of Arty A7 DDR3 documentation and from this tutorial.
Edited by Viktor NikolovThe difference is that I'm using an external 100 MHz clock for the MIG input System Clock instead of the 166.67 MHz recommended in Arty A7 documentation. Using an internally generated clock for MIG System Clock is strongly not recommended by Xilinx documentation (I received this feedback on the Xilinx support forum).
I explain this topic in more detail here.
Added info about Vivado 2024.1
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