Zynq Board Eclypse-Z7 pinout warning

[Deffe]

Just want to remark this anomaly between the pinout list from AMD (Xilinx) and the Eclipse-Z7 XDC and schematic files.
These are the pinout of the PMOD headers as is given in the XDC file for the board

Quote

The “IOSTANDARD LVCMOS33” is removed from within the -dict brackets to get the constraint lines on on text line.

#- Pmod Header JA in IO-Bank 35
#-
#- set_property -dict { PACKAGE_PIN B15 } [get_ports { ja[0] }];    #- IO_0_35                   Sch=ja1_fpga
#- set_property -dict { PACKAGE_PIN C15 } [get_ports { ja[1] }];    #- IO_25_35                  Sch=ja2_fpga
#- set_property -dict { PACKAGE_PIN D15 } [get_ports { ja[2] }];    #- IO_L1N_T0_AD0N_35         Sch=ja3_fpga
#- set_property -dict { PACKAGE_PIN E16 } [get_ports { ja[3] }];    #- IO_L1P_T0_AD0P_35         Sch=ja4_fpga
#- set_property -dict { PACKAGE_PIN E15 } [get_ports { ja[4] }];    #- IO_L2N_T0_AD8N_35         Sch=ja7_fpga
#- set_property -dict { PACKAGE_PIN F17 } [get_ports { ja[5] }];    #- IO_L2P_T0_AD8P_35         Sch=ja8_fpga
#- set_property -dict { PACKAGE_PIN F16 } [get_ports { ja[6] }];    #- IO_L3N_T0_DQS_AD1N_35     Sch=ja9_fpga
#- set_property -dict { PACKAGE_PIN G16 } [get_ports { ja[7] }];    #- IO_L3P_T0_DQS_AD1P_35     Sch=ja10_fpga

#- Pmod Header JB in IO-Bank 35
#-
#- set_property -dict { PACKAGE_PIN G15 } [get_ports { jb[0] }];  #- IO_L4N_T0_35              Sch=jb1_fpga
#- set_property -dict { PACKAGE_PIN D16 } [get_ports { jb[1] }];  #- IO_L4P_T0_35              Sch=jb2_fpga
#- set_property -dict { PACKAGE_PIN D17 } [get_ports { jb[2] }];  #- IO_L5N_T0_AD9N_35         Sch=jb3_fpga
#- set_property -dict { PACKAGE_PIN E18 } [get_ports { jb[3] }];  #- IO_L5P_T0_AD9P_35         Sch=jb4_fpga
#- set_property -dict { PACKAGE_PIN F18 } [get_ports { jb[4] }];  #- IO_L6N_T0_VREF_35         Sch=jb7_fpga
#- set_property -dict { PACKAGE_PIN G17 } [get_ports { jb[5] }];  #- IO_L6P_T0_35              Sch=jb8_fpga
#- set_property -dict { PACKAGE_PIN H18 } [get_ports { jb[6] }];  #- IO_L7N_T1_AD2N_35         Sch=jb9_fpga
#- set_property -dict { PACKAGE_PIN H17 } [get_ports { jb[7] }];  #- IO_L7P_T1_AD2P_35         Sch=jb10_fpga

The above text from the constraints file is also how things are pictured in the schematics of the Eclypse-Z7 board.

BUT: The pin numbers might be correct the description of the pin function is wrong for some pins! It is wrong in the XDC file and also in the schematics (page 8 of 15)

This is the pin numbering and pin function description as is is provided in the Xilinx pinlist obtained from the “Zynq 7000 SoC Packaging and Pinout Specification” (UG865) page 27 entitled “ASCII Pinout Files”. Link CLG484 in table 2-1

This is the pinning of PMOD JA

 F16   IO_L1P_T0_AD0P_35         IO-Bank 35
    E16   IO_L1N_T0_AD0N_35         IO-Bank 35
    E15   IO_L3P_T0_DQS_AD1P_35     IO-Bank 35
    D15   IO_L3N_T0_DQS_AD1N_35     IO-Bank 35
    G16   IO_L4N_T0_35              IO-Bank 35
    F17   IO_L6N_T0_VREF_35         IO-Bank 35
    C15   IO_L7P_T1_AD2P_35         IO-Bank 35
    B15   IO_L7N_T1_AD2N_35         IO-Bank 35

This is the pinning of PMOD JB

 H17   IO_0_35                   IO-Bank 35
    D16   IO_L2P_T0_AD8P_35         IO-Bank 35
    D17   IO_L2N_T0_AD8N_35         IO-Bank 35
    G15   IO_L4P_T0_35              IO-Bank 35
    F18   IO_L5P_T0_AD9P_35         IO-Bank 35
    E18   IO_L5N_T0_AD9N_35         IO-Bank 35
    G17   IO_L6P_T0_35              IO-Bank 35
    H18   IO_25_35                  IO-Bank 35

The pin information, being pin number to its function, is for boyj PMOD connector completely mingled. One example of what’s wrong:

The Eclypse-Z7 XDC file list pin B15 of PMOD JA as having the function IO_0_35

While the Xilinx pin information lists that function to pin H17 fixed in PMOD JB

Please review the XDC and schematics (schematic symbol of the FPGA).

Thanks

[zygot]

Digilent has some good engineers on staff. I'm just not sure what exactly it is that they do. They never review published Digilent documentation like reference manuals or constraint files for errors. It took me over 2 years of prodding to get them to fix the Genesys2 reference manual and constraints file, which had the incorrect pin assignments for it's PMOD headers. Anyone could see that someone had just modified the Nexys Video documentation and done a very bad job of it; no one checks the work of farmed out labor. This just has never been a priority for them.

Here are two versions of the same file published by Digilent that I found on my development PC.

Eclypse-Z7-Master dated 2/12/2020
## Pmod Header JA
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0 Sch=ja1_fpga
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_25 Sch=ja2_fpga
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L1N_T0_AD0N Sch=ja3_fpga
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L1P_T0_AD0P Sch=ja4_fpga
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L2N_T0_AD8N Sch=ja7_fpga
#set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L2P_T0_AD8P Sch=ja8_fpga
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L3N_T0_DQS_AD1N Sch=ja9_fpga
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L3P_T0_DQS_AD1P Sch=ja10_fpga

## Pmod Header JB
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L4N_T0 Sch=jb1_fpga
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L4P_T0 Sch=jb2_fpga
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L5N_T0_AD9N Sch=jb3_fpga
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L5P_T0_AD9P Sch=jb4_fpga
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L6N_T0_VREF Sch=jb7_fpga
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L6P_T0 Sch=jb8_fpga
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L7N_T1_AD2N Sch=jb9_fpga
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L7P_T1_AD2P Sch=jb10_fpga

Eclypse-Z7-Master dated 11/02/2023
## Pmod Header JA
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0 Sch=ja1_fpga
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_25 Sch=ja2_fpga
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L1N_T0_AD0N Sch=ja3_fpga
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L1P_T0_AD0P Sch=ja4_fpga
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L2N_T0_AD8N Sch=ja7_fpga
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L2P_T0_AD8P Sch=ja8_fpga
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L3N_T0_DQS_AD1N Sch=ja9_fpga
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L3P_T0_DQS_AD1P Sch=ja10_fpga

## Pmod Header JB
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L4N_T0 Sch=jb1_fpga
#set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L4P_T0 Sch=jb2_fpga
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L5N_T0_AD9N Sch=jb3_fpga
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L5P_T0_AD9P Sch=jb4_fpga
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L6N_T0_VREF Sch=jb7_fpga
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L6P_T0 Sch=jb8_fpga
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L7N_T1_AD2N Sch=jb9_fpga
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L7P_T1_AD2P Sch=jb10_fpga

As far as I know, the only schematic with errors, other than commentary like pin function, is the NetFPGA-1G-CML which, thankfully, Digilent no longer sells. The same can't be said for reference manuals and constraints files, where I've come across lots of errors; and not just pin function comments, but actual pin assignment errors for a number of their boards. The company just doesn't have the kind of professional standards and processes that you'd expect from a vendor.

It's certainly worrisome when even the schematics have errors, even when they are simply pin function and don't necessarily affect the design process.

Just a reminder that the user is responsible for confirming that the information that they read from a vendor needs to be checked for errors. Do go by the official AMD/Xilinx documentation for pin function. Don't rely on master constraints files to be correct, especially if they're from Digilent. If you find errors in a schematic, then consider if you really want to waste your time with a product. Edited November 27, 2023 by zygot

[artvvb]

Hi @Deffe

The constraint comments have been fixed in the digilent-xdc repo and I've confirmed that the schematic pin names are correct. I've attached the spreadsheet used to compare against xc7z020clg484pkg.txt, in case you want to double-check.

Eclypse Pmod Constraints.xlsx

Thanks,

Arthur

[mikemikemike]

Hmm some of the confusion here might be , per the comments in xdc file, the ja references in the XDC are numbered differently to the corresponsing JA references on the schematic. ie ja[0] in the XDC appears as JA1 on the schematic, i.e. the ja numbering goes [0:7] in the XDC but those 8 lines map to JA[1:4] and JA[7:10] since JA[5:6] and JA[11:12]  are used for pairs of VCC and GND connections on the PMOD connectors, i.e pins 5 and 11 are GND and pins 6 and 12 are VCC3V3 on JA