I've been encountering this error every time I have tried to run implementation of my modules on Verilog. I've looked into previous error flags related to this but the solutions aren't really working. I'll link my current .xdc file with it's constraints here.
Here's the error:
[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clr_IBUF] >
clr_IBUF_inst (IBUF.O) is locked to IOB_X1Y48 and clr_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y14
From what I can understand, the error appears to be centered around my CLK100MHZ which is being used for my joystick input. I don't really understand why though, the W5 pin I've assigned from the reference with the official BASYS3 reference is correct as it is the only 100MHZ clock pin. Which means I doubt the error is because of the I/O assignment.
When I use the given constraint addition to demote this from an error to a warning, the implementation works and the bitstream is generated - but there is no VGA output and my program doesn't work. I'm not sure if this is related to this error or if it is because of some other reason. And as a result debugging has become a nightmare. For reference, I have an old bitstream of before I attempted to integrate my code with the joystick, and my code was giving a vga output then. So I'm not sure what could have broken it except for the fact that the clock signal isn't working. If anyone could provide any advice whatsoever I'd really appreciate it.
I'm not really sure what would help in debugging this, so if any files are necessary for you guys I'll be happy to provide them. As of right now, I'm completely lost on what to do.
Question
Reckon1ng
I've been encountering this error every time I have tried to run implementation of my modules on Verilog. I've looked into previous error flags related to this but the solutions aren't really working. I'll link my current .xdc file with it's constraints here.
Here's the error:
[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clr_IBUF] >
clr_IBUF_inst (IBUF.O) is locked to IOB_X1Y48 and clr_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y14
From what I can understand, the error appears to be centered around my CLK100MHZ which is being used for my joystick input. I don't really understand why though, the W5 pin I've assigned from the reference with the official BASYS3 reference is correct as it is the only 100MHZ clock pin. Which means I doubt the error is because of the I/O assignment.
When I use the given constraint addition to demote this from an error to a warning, the implementation works and the bitstream is generated - but there is no VGA output and my program doesn't work. I'm not sure if this is related to this error or if it is because of some other reason. And as a result debugging has become a nightmare. For reference, I have an old bitstream of before I attempted to integrate my code with the joystick, and my code was giving a vga output then. So I'm not sure what could have broken it except for the fact that the clock signal isn't working. If anyone could provide any advice whatsoever I'd really appreciate it.
I'm not really sure what would help in debugging this, so if any files are necessary for you guys I'll be happy to provide them. As of right now, I'm completely lost on what to do.
myconst.xdc
XADCdemo.v NERP_demo_top.v vga640x480.v bird.v
Edited by Reckon1ngAdded more files
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