Error for poor placing between IO and BUFG? No idea what to do

[Reckon1ng]

I've been encountering this error every time I have tried to run implementation of my modules on Verilog. I've looked into previous error flags related to this but the solutions aren't really working. I'll link my current .xdc file with it's constraints here.

Here's the error:

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clr_IBUF] >

clr_IBUF_inst (IBUF.O) is locked to IOB_X1Y48 and clr_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y14

From what I can understand, the error appears to be centered around my CLK100MHZ which is being used for my joystick input. I don't really understand why though, the W5 pin I've assigned from the reference with the official BASYS3 reference is correct as it is the only 100MHZ clock pin. Which means I doubt the error is because of the I/O assignment.

When I use the given constraint addition to demote this from an error to a warning, the implementation works and the bitstream is generated - but there is no VGA output and my program doesn't work. I'm not sure if this is related to this error or if it is because of some other reason. And as a result debugging has become a nightmare. For reference, I have an old bitstream of before I attempted to integrate my code with the joystick, and my code was giving a vga output then. So I'm not sure what could have broken it except for the fact that the clock signal isn't working. If anyone could provide any advice whatsoever I'd really appreciate it.

I'm not really sure what would help in debugging this, so if any files are necessary for you guys I'll be happy to provide them. As of right now, I'm completely lost on what to do.

myconst.xdc

XADCdemo.v NERP_demo_top.v vga640x480.v bird.v

Edited November 25, 2023 by Reckon1ng
Added more files

[zygot]

When you have no idea how to resolve a problem, then perhaps it's time to read the instructions.

In this case the 'instructions" are in the Series 7 reference manuals, where descriptions of how the FPGA resources are organized, how they work, and what limitations for their use might have an impact on your design flow. So read though the Clocking and Select IO users guides. You can find them in the Documentation Navigator that was installed with Vivado.

All FPGA devices have some manner of clock regions due to limited resources. Intel Cyclone devices have more restrictive clock region rules, so boards using those devices tend to have more external clock sources to cover the whole device. Series 7 devices have a different clocking architecture, but still have limitations. Often one external clock is sufficient to implement simple designs. Digilent. in order to cut costs, has always provided the minimal number of external clocks possible, which is often unsuitable for more complicated designs. When you are using IO pins on every IO bank this complicates clock resource placements, like buffers.

I suspect that the tool version has something to do with the placer error that you received; I frequently run into this using recent tool versions but don't remember do so with older tool versions.

You can try following the suggestion of the tools and add the constraint to your design. You can also manually place logic and clock resources, such as buffers and MMCM/PPL blocks. Whatever approach you take, you will be responsible for making timing closure, if it's a problem.

[Reckon1ng]

9 hours ago, zygot said:

When you have no idea how to resolve a problem, then perhaps it's time to read the instructions.

In this case the 'instructions" are in the Series 7 reference manuals, where descriptions of how the FPGA resources are organized, how they work, and what limitations for their use might have an impact on your design flow. So read though the Clocking and Select IO users guides. You can find them in the Documentation Navigator that was installed with Vivado.

All FPGA devices have some manner of clock regions due to limited resources. Intel Cyclone devices have more restrictive clock region rules, so boards using those devices tend to have more external clock sources to cover the whole device. Series 7 devices have a different clocking architecture, but still have limitations. Often one external clock is sufficient to implement simple designs. Digilent. in order to cut costs, has always provided the minimal number of external clocks possible, which is often unsuitable for more complicated designs. When you are using IO pins on every IO bank this complicates clock resource placements, like buffers.

I suspect that the tool version has something to do with the placer error that you received; I frequently run into this using recent tool versions but don't remember do so with older tool versions.

You can try following the suggestion of the tools and add the constraint to your design. You can also manually place logic and clock resources, such as buffers and MMCM/PPL blocks. Whatever approach you take, you will be responsible for making timing closure, if it's a problem.

Thank you for the reply, I had been using the constraint but the issue of there being no vga output persisted.

 

Alas, I managed to get rid of the error with a lot of trial and error and got lucky with some changes in my code.

 

Unfortunately however, my VGA output signal is not working. nerp_demo_top is instantiated under XADC demo, and when I set nerp_demo_too as the top module, the screen does work and the output is received, but once I set XADCdemo as top it no longer does.

 

I'm still pretty lost on this, everything seemingly is correct. My only working theory is that there's still some unknown logic error with the 100mhz clock.

[zygot]

Usually, Vivado is able to figure out what the toplevel entity or module in a design is. When it can't, that's a sign of something wrong. You can always set any of your source files as toplevel manually. Be sure that the toplevel module port signal names are identical to those in your constraints file.

The correct way to do the HDL design flow is to write a testbench for every module in your design. At least start out with a testbench for your toplevel design. Simulation should help identify problems. Writing code and trying it out on hardware to see if it works is a really bad way to do FPGA design. Edited November 26, 2023 by zygot

[artvvb]

Hi @Reckon1ng

The NERP_demo_top module instantiation is missing the ground_touch input. Assignment of signals in a module instantiation using an ordered list instead of explicitly using the names of the module ports is an easy way to introduce errors. In this case, the clock is being connected to the logic associated with the ground_touch input which causes something that doesn't meet the FPGA architecture's requirements to happen.

Try this in XADCdemo.v:

NERP_demo_top flap1 (
	.jump_btn       (up),
	.down_btn       (down),
	.enable_btn     (enable_btn),
	.rst_btn        (rst_btn),
	.jumprate1      (c1),
	.jumprate2      (c2),
	.jumprate3      (c3),
	.ground_touch   (), // Not driven, tie high or low (1'b1 or 1'b0 inside the parentheses), or connect to some other signal
	.clk            (CLK100MHZ),
	.clr            (clr),
	.seg            (seg),
	.an             (an),
	.dp             (dp),
	.red            (red),
	.green          (green),
	.blue           (blue),
	.hsync          (hsync),
	.vsync          (vsync)
);

Edit: For debugging purposes for catching this kind of thing, reviewing the design in Vivado's RTL Elaboration -> Schematic view can be helpful.

Thanks,

Arthur