Eclypse DDR Streaming Project channel calibration question

Xband · October 24, 2023

I have this hardware and software running and giving output on the serial port. When I run the calibration routine it seems to give reasonable data but when I run the S2MM code the output seems to be in hex. My guess is that the cal file isn't referenced properly but its a guess and I can't seem to locate where a file such as this is read in the code, I see the scope_calibration.c file Below are the serial result of the calibration_reader_system and s2mm_cyclic_transfer_test_system.

Eventually I want to perform some math on channel acquisitions and spit out a result. I've input a 1kHz +/- 1V sine wave but direct conversion from hex to decimal in Exce (sorry I hate it too) gives nonsense huge numbers column H & I converting B and C.

Thanks for any insight.

========= Zmod Port A : Zmod ADC 1410-105 Calibration Coefficients =========

Factory Calibration: December 24, 2021 at 02:55:34
CHAN_1_LG_GAIN: -0.000055
CHAN_1_LG_OFFSET: -0.076329
CHAN_1_HG_GAIN: 0.011868
CHAN_1_HG_OFFSET: -0.002765
CHAN_2_LG_GAIN: -0.001325
CHAN_2_LG_OFFSET: 0.130576
CHAN_2_HG_GAIN: 0.010189
CHAN_2_HG_OFFSET: 0.006026
Ch1LgCoefMultStatic: 0x10CC9
Ch1LgCoefAddStatic: 0x3FE71
Ch1HgCoefMultStatic: 0x11951
Ch1HgCoefAddStatic: 0x3FE97
Ch2LgCoefMultStatic: 0x10C72
Ch2LgCoefAddStatic: 0x002AD
Ch2HgCoefMultStatic: 0x118D9
Ch2HgCoefAddStatic: 0x00316

User Calibration: December 24, 2021 at 02:55:34
CHAN_1_LG_GAIN: -0.000055
CHAN_1_LG_OFFSET: -0.076329
CHAN_1_HG_GAIN: 0.011868
CHAN_1_HG_OFFSET: -0.002765
CHAN_2_LG_GAIN: -0.001325
CHAN_2_LG_OFFSET: 0.130576
CHAN_2_HG_GAIN: 0.010189
CHAN_2_HG_OFFSET: 0.006026
Ch1LgCoefMultStatic: 0x10CC9
Ch1LgCoefAddStatic: 0x3FE71
Ch1HgCoefMultStatic: 0x11951
Ch1HgCoefAddStatic: 0x3FE97
Ch2LgCoefMultStatic: 0x10C72
Ch2LgCoefAddStatic: 0x002AD
Ch2HgCoefMultStatic: 0x118D9
Ch2HgCoefAddStatic: 0x00316

Done initializing device drivers
TestMode: 0
Initialization done
ADC initialization done
Waiting for trigger...
Last beat found:
BD base address: 00124168
BD actual length: 0000000C
Buffer base address: 00124168
Buffer high address: 00128164
Length of buffer (words): 4096
Index of buffer head: 3
Trigger position: 0
Index of trigger position: 3
Detected trigger condition: 00000002
Transfer done
@00124174 FFE70007 3FF9 0001 0 3
@00124178 FFECFFFF 3FFB 3FFF 0 -3
@0012417C FFF0FFEE 3FFC 3FFB 0 -15
@00124180 FFE7FFFF 3FF9 3FFF 0 -3
@00124184 FFDE0003 3FF7 0000 -1 0
@00124188 FFDEFFEA 3FF7 3FFA -1 -18
@0012418C FFD60003 3FF5 0000 -1 0
@00124190 FFDE0003 3FF7 0000 -1 0
@00124194 FFDAFFEA 3FF6 3FFA -1 -18
@00124198 FFEC0003 3FFB 0000 0 0
@0012419C FFECFFFF 3FFB 3FFF 0 -3
@001241A0 FFDA0003 3FF6 0000 -1 0
@001241A4 FFE3FFFB 3FF8 3FFE 0 -6
@001241A8 FFECFFF6 3FFB 3FFD 0 -9
@001241AC 036C0003 00DB 0000 26 0
@001241B0 0BD20035 02F4 000D 92 39
@001241B4 0A9100D5 02A4 0035 82 161
@001241B8 04E60157 0139 0055 38 259
@001241BC 049C0191 0127 0064 36 305
@001241C0 055D01AB 0157 006A 41 323
@001241C4 0611019A 0184 0066 47 311
@001241C8 064601AF 0191 006B 48 326
@001241CC 066901BB 019A 006E 50 335
@001241D0 06B401C0 01AD 0070 52 341
@001241D4 06FF01BB 01BF 006E 54 335
@001241D8 073C01C8 01CF 0072 56 347
@001241DC 078201BB 01E0 006E 58 335
@001241E0 07CD01DD 01F3 0077 60 363
@001241E4 082101E5 0208 0079 63 369
@001241E8 087401DD 021D 0077 66 363
@001241EC 08CC0

artvvb · November 20, 2023

No loops or reduced jogs may help somewhat with the interface routing mess. No loops makes it harder to tell at a glance what pins/interfaces are inputs and which are outputs. The regenerate layout button will also shuffle everything around to try to fit it on screen, which is a blessing and a curse.

zygot · November 21, 2023

Xband: "You should play tennis if you enjoy watching others suffer. :)"

I used to play tennis.. to the amusement of everyone but me...

No, I don't like to see people suffer. I just wish that either Digilent would honestly advertise the Eclypse-Z7 or change the support to match the marketing claims.

Since I don't like to suffer, I've just moved on to other platforms for using my Zmod ADC/DAC pods. Life's too short to struggle with unnecessary complexity and design short-comings.

You are aware of the discrepancy between Digilent's support of the Eclypse-Z7 for customers and their own proprietary Waveforms implementation for the same platform, right?
But even Digilent Engineers, as the slow roll-out for Waveforms support of this board demonstrates, can't do "rapid development" for it's own board.

Xband · November 30, 2023

@zygot

I'm happy that they are producing this hardware as its performance fills a gap in what is available otherwise. I can't blame Digilent for not providing basic Xilinx FPGA training, they have basic documentation that not any worse than what Xilinx has to offer. The Xilinx documentation seems to be written to "have something" which is a common ideology but might not actually produce much help.

For me I"m struggling with basic issues when trying to add or modify the diligent code, my main accomplishment has been being able to change the sample rate on the ADC, which is instructive.

I'm not in a position to be able to reproduce the code that's available so that is how I must learn at this point.

Edited November 30, 2023 by Xband
spelling

Xband · November 30, 2023

@artvvb

After looking at this issue more it would seem that a DSP Accumulator should do the job of integrating the data from the ADC in a timely manner. I've tried finding examples that I can relate to the project but I cannot figure out where exactly to place the Acummulator Ip nor is it clear what type of data should be fed into this thing.

I'm not sure where to connect a wire from the Axi4 Fifo created for the other method, the bit structure does not match and I cannot change it from 16 bits in the accumulator ip. ( I actually figured out how to change the input bit width since posting, you have to move a slider from Automatic to manual)

Do I need to use a slice function and perhaps another accumulator for the second channel?

The best example I found that this should work was from Labview FPGA (sorry) it seems that for an array it is adding even or odd values every other clock cycle. I couldn't find anything on the Xilinx site that shows a block diagram connection for these.

https://www.ni.com/docs/en-US/bundle/labview-fpga-module/page/lvfpga/ht_accumulator.html

Trigger level high:

I'll also need a digital level that stays high for the entire acquisition of ADC trigger. Perhaps there is one coming out of the trigger generator that you could suggest.

I'll probably need to create a variable to extract the accumulator result, perhaps I could put it in the level trigger software in vitus and send the result out instead of or along with the ADC sample result.

Sorry to change horses again before getting to far into the stream but it is implied that this should be a fast way to integrate the data, implied by FFT results using the DSP.

Thanks,

Edited November 30, 2023 by Xband
Figured out how to edit Accumulator input width

Xband · November 30, 2023

If you're at all interested by this Labview implementation of FPGA this IP look at this link where Labview spawns the Vivado custom IP windows, they give a decent explanation of whats goin on and the example vi shows 3 different fifo's.

https://knowledge.ni.com/KnowledgeArticleDetails?id=kA03q000001E0NFCA0&l=en-US

artvvb · November 30, 2023

Hi XBand,

I'm actively taking a look through this and will have some more comments later this afternoon. Trying to break down the problem in a way that steps back a bit from the context of the DDR streaming demo, since I think that it is making things more complicated than needed. That said, some of the material in the demo project is still extremely necessary.

The LabVIEW material looks interesting. A colleague also mentioned MATLAB, Simulink, and Model Composer as an option for this kind of DSP, but I have not used it myself, and it requires some licenses that you may or may not have access to.

An accumulator will be able to perform the integration - this IP looks reasonable for it. Note that the output width probably needs to be large enough to fit the number 0xffff * 700 (assuming 700 us at 100 MS/s), so minimum 26 bits.

Quote

Do I need to use a slice function and perhaps another accumulator for the second channel?

Yes, it will be easier to treat each channel separately. Slicing off one of the channels so you can focus on designing the system for only one of them would also be appropriate. Also, you can treat tvalid on the AXI stream interface as an enable pin for downstream logic, as long as that logic needs to be run once every cycle - if you don't need extra control logic for the accumulator, maybe it's clock enable could just be tied to tvalid, for example.

Would getting those scope captures of what a pulse looks like be possible? The paint diagrams below illustrate how I'm currently thinking about the shape of the pulses and timing:

Charge threshold and voltage threshold would be specified separately.

Thanks,

Arthur

artvvb · December 1, 2023

I'm really sorry, I was caught up with several other tasks today.

5 hours ago, Xband said:

I'll also need a digital level that stays high for the entire acquisition of ADC trigger. Perhaps there is one coming out of the trigger generator that you could suggest.

The trigger outputs stay high for one stream beat (one clock cycle). Additional hardware that could handle this would be a register that gets set when the trigger output is high, paired with a counter that counts until it reaches a predefined value at which point the register clears, functionally a pulse extender/stretcher.

artvvb · December 1, 2023

As an example of writing an RTL module from scratch, the following is the pulse extender described above.

Design source:

`timescale 1ns / 1ps

module extend_pulse #(
    parameter integer LENGTH = 10
) (
    input wire clk,
    input wire resetn,
    input wire trigger_in,
    output wire extended_trigger_out
);
    reg trigger_reg = 'b0;
    reg [$clog2(LENGTH-1)-1:0] counter = 'b0;
    
    // Register, set when trigger_in is high, clear LENGTH clock cycles later
    always @(posedge clk) begin
        if (resetn == 1'b0) begin
            trigger_reg <= 'b0;
        end else if (trigger_reg == 1'b0) begin
            trigger_reg <= trigger_in;
        end else begin // if trigger_reg == 1'b1
            if (counter >= LENGTH-1) begin
                trigger_reg <= trigger_in;
            end // else stay high
        end
    end 
    
    // Counter, clear when trigger_in is high, else increment when trigger_reg is high 
    always @(posedge clk) begin
        if (resetn == 1'b0) begin
            counter <= 'b0;
        end else if (trigger_in == 1'b1) begin
            counter <= 'b0;
        end else if (trigger_reg == 1'b1) begin
            counter <= counter + 1'b1;     
        end
    end
    
    assign extended_trigger_out = trigger_reg;
endmodule

Simulation source:

`timescale 1ns / 1ps

module pulse_sim;
    reg clk = 1'b0;
    initial begin
        #10 clk = 1'b1;
        forever #5 clk = ~clk;
    end
    
    reg resetn = 1'b0;
    initial begin
        // clear on the first clock edge
        @(posedge clk) resetn <= 1'b1;
    end
    
    reg trigger_in = 0;
    
    initial begin
        #400 trigger_in <= 1'b1;
        #20 trigger_in <= 1'b0;
    end
    
    wire trigger_out;
    
    extend_pulse #(
        .LENGTH(10)
    ) dut (
        .clk(clk),
        .resetn(resetn),
        .trigger_in(trigger_in),
        .extended_trigger_out(trigger_out)
    );
endmodule

Simulation results, showing the extended pulse going for an additional 10 clock cycles after the pulse:

And a guide for simulation, which ought to let you reproduce the above: https://digilent.com/reference/programmable-logic/guides/simulation

Xband · December 1, 2023

This is a basic representation of the signals to capture. The integration will take place over multiple pulses typically at 30Hz.

Xband · December 9, 2023

Similar names were causing problems, have RTL pulse extender added now.

I've done this multiple times and it seems that every time I create this source it turns out to be a "hidden incompatible module".

Cannot figure out what I"m doing wrong, have looked up multiple examples it does not seem to work.

Did you mean for me to do a simulation? I was working under the impression that your sim should be good.

I've tried creating it as Verilog and VHDL (from Adding Sources) with the same problem.

Any idea?

Edited December 9, 2023 by Xband

artvvb · December 11, 2023

This list is made up of "module name (filename)" pairs, and two module names in the list match. One of the files needs to be edited to change the module name so that Vivado can tell which module should be used when it is instantiated in other sources.

Xband · December 12, 2023

@artvvb thanks, I figured that out immediately after I posted the question,

my next struggle is appending the accumulated data into the Axi stream. I would like to arrange the data (ch1value, ch1 integrated , ch2 data, Ch2 integrated). I’ve concat’ed these values into a bit representation but cannot figure out how to insert/ replace this into the existing AXI stream.

I’ll post a block diagram screenshot when I can, I’m a bit concerned this will cause problems with the existing code, will need to adjust Axi stream bit address in downstream I’m guessing.

Should I greate a separate AXI stream for this appended data?

artvvb · December 12, 2023

The DMAs are configured to handle 32-bit streams, increasing the width is possible, but would likely make it so that samples might be dropped. Adding another DMA configured to receive another 32-bit AXI stream is possible but involved.

1. How many bits wide are the concatenated stream and the accumulator outputs?

2. Do you *need* to move data from both channels and both accumulators into DDR, or is it acceptable to only send some of it up?

Even using all of the AXI stream signals wouldn't be necessary if you aren't trying to pass stuff to the processor - the ready signal in the interface passing data to your logic could be tied high (or to a software enable bit if there isn't another one further upstream), and the valid signal could be used as an enable for your logic.

Xband · December 15, 2023

@artvvb

Just as a proof of concept now I would replace the "channel 2" data signal with the Accumulator sum for testing. I've tried to configure the sum as 16 bit so the concat'ed data is 32 bits, so it should fit back into the AXI stream.

On 12/12/2023 at 3:16 PM, artvvb said:

The DMAs are configured to handle 32-bit streams, increasing the width is possible, but would likely make it so that samples might be dropped. Adding another DMA configured to receive another 32-bit AXI stream is possible but involved.

1. How many bits wide are the concatenated stream and the accumulator outputs?

2. Do you *need* to move data from both channels and both accumulators into DDR, or is it acceptable to only send some of it up?

1. Sum and original ADC value for channel 1 should be 32 bits,

2. For the final project there are a couple of options, the Accumulator data is needed, it would be nice to be able to store up to 10 pulses for each channel. The pulses could be buffered into memory.

Cannot seem to find an instruction for entering data into the axi stream. This seems pretty basic. Most of the tutorials are regurgitation of Xilinx documents without examples of actually doing this. Even in the DSP examples they all end up using it fancy IP that has the AXI out.

Looking at the code it almost seems like some are connecting the data bitstream to the AXI clock signal, maybe this is an obvious solution to more experienced users.

Now I'm looking screen mining IP looking for the axi_td_data in signal which seems like it would be the correct input.

Thanks,

image.png.2584970057fc72bde7e4ebeae7616768.png

artvvb · December 15, 2023

You can manually wire ports within interfaces to other ports, the interfaces expand with the "+" button on the IP. Be aware of how clock signals are used. Latency through various modules will affect how accumulator data and adc data are aligned in the stream.

For what it's worth, the following is the code for the create_tlast module in the above screenshot, which just ties the tlast of the m interface low.

Quote

`timescale 1ns / 1ps

module create_tlast(
input wire aclk,
input wire resetn,

output wire s_tready,
input wire s_tvalid,
input wire [31:0] s_tdata,

input wire m_tready,
output wire m_tvalid,
output wire [31:0] m_tdata,
output wire m_tlast
);
assign s_tready = m_tready;
assign m_tvalid = s_tvalid;
assign m_tdata = s_tdata;
assign m_tlast = 1'b0;
endmodule

Xband · December 26, 2023

@artvvb,

Realize its the holidays, throwing this out whenever you can have a look or anyone else following.

I"m still trying to diagnose. Synthesis and implementation pass. Quite a few ip upgrade errors.

Bitstream failed to generate,

Thanks,

ERROR: [DRC NSTD-1] Unspecified I/O Standard: 171 out of 171 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: beat_count[31:0], error_count[31:0], m_tdata[31:0], miss_count[31:0], s_tdata[31:0], clk, decouple_streams, idle, m_tlast, m_tready, m_tvalid, resetn, s_tlast, s_tready, s_tvalid... and (the first 15 of 16 listed).
ERROR: [DRC UCIO-1] Unconstrained Logical Port: 171 out of 171 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: beat_count[31:0], error_count[31:0], m_tdata[31:0], miss_count[31:0], s_tdata[31:0], clk, decouple_streams, idle, m_tlast, m_tready, m_tvalid, resetn, s_tlast, s_tready, s_tvalid... and (the first 15 of 16 listed).
WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
INFO: [Vivado 12-3199] DRC finished with 2 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 2 Warnings, 0 Critical Warnings and 3 Errors encountered.
write_bitstream failed
ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.

INFO: [Common 17-206] Exiting Vivado at Tue Dec 26 12:21:30 2023...

[DRC NSTD-1] Unspecified I/O Standard: 171 out of 171 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: beat_count[31:0], error_count[31:0], m_tdata[31:0], miss_count[31:0], s_tdata[31:0], clk, decouple_streams, idle, m_tlast, m_tready, m_tvalid, resetn, s_tlast, s_tready, s_tvalid... and (the first 15 of 16 listed).

Xband · December 26, 2023

See this response, I didn't change any port definitions from the baseline DDR project though, I think mine has more to do with the AXI stream perhaps, let me know....

artvvb · December 26, 2023

Please check your block design sources tab, it should look something like the image below. Note that there are several files in the design sources. In this case (I don't have the same project open), there is a block design file (.bd), which is listed under an HDL top module (_wrapper.v). The wrapper file should be bolded, which indicates that it has been selected as the top layer of the design. RTL modules used in the design (like the test.v file in the screenshot) may be listed underneath the wrapper at the top level of the hierarchy, or nested underneath the block design file somewhere.

These errors indicate to me that a different file has been selected as the top module, and the port names used in the constraints don't match what that top module expects - and the port names all match what I'd expect from one of the RTL modules in the design. Make sure the top module is actually a block design wrapper. This could happen if using checkout scripts in a Vivado version that is incompatible - in that case, the block design might only be partially complete or empty, where a wrapper can't be automatically created.

Xband · December 27, 2023

Hi @artvvb,

updated the top design wrapper, now getting "[Synth 8-439] module 'design_1_create_tlast_0_0' not found" for a few IP's. I've tried adding IP from sources a few times and installed y2k22_patch, which pops up as a reason for this in earlier versions.

Thanks for any input. Probably something stupid I did along the way. Seems to be an infinite number of ways to make this process difficult!

image.png.938dacd1aabe065d335c5e55160f7965.png

WARNING: [Runs 36-337] The following IPs are either missing output products or output products are not up-to-date for Implementation target. Since these IPs are locked, no update to the output products can be done.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
C:/Users/LENOVO/Documents/GitHub/hw/hw.srcs/sources_1/bd/design_1/design_1.bd

[Wed Dec 27 11:18:21 2023] Launched design_1_processing_system7_0_0_synth_1, design_1_c_accum_1_0_synth_1, design_1_c_accum_0_2_synth_1, design_1_axi_fifo_mm_s_0_0_synth_1, design_1_axis_register_slice_0_1_synth_1, design_1_extend_pulse_0_0_synth_1, design_1_create_tlast_0_0_synth_1...
Run output will be captured here:
design_1_processing_system7_0_0_synth_1: C:/Users/LENOVO/Documents/GitHub/hw/hw.runs/design_1_processing_system7_0_0_synth_1/runme.log
design_1_c_accum_1_0_synth_1: C:/Users/LENOVO/Documents/GitHub/hw/hw.runs/design_1_c_accum_1_0_synth_1/runme.log
design_1_c_accum_0_2_synth_1: C:/Users/LENOVO/Documents/GitHub/hw/hw.runs/design_1_c_accum_0_2_synth_1/runme.log
design_1_axi_fifo_mm_s_0_0_synth_1: C:/Users/LENOVO/Documents/GitHub/hw/hw.runs/design_1_axi_fifo_mm_s_0_0_synth_1/runme.log
design_1_axis_register_slice_0_1_synth_1: C:/Users/LENOVO/Documents/GitHub/hw/hw.runs/design_1_axis_register_slice_0_1_synth_1/runme.log
design_1_extend_pulse_0_0_synth_1: C:/Users/LENOVO/Documents/GitHub/hw/hw.runs/design_1_extend_pulse_0_0_synth_1/runme.log
design_1_create_tlast_0_0_synth_1: C:/Users/LENOVO/Documents/GitHub/hw/hw.runs/design_1_create_tlast_0_0_synth_1/runme.log
[Wed Dec 27 11:18:23 2023] Launched synth_1...

Edited December 27, 2023 by Xband

Xband · December 27, 2023

report_ip_status,

Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
| Date : Wed Dec 27 11:54:12 2023
| Host : DESKTOP-A1N1QKI running 64-bit major release (build 9200)
| Command : report_ip_status
---------------------------------------------------------------------------------------------------------------------------------------------

IP Status Summary

1. Project IP Status
--------------------
Your project uses 142 IP. Some of these IP may have undergone changes in this release of the software. Please review the recommended actions.

More information on the Xilinx versioning policy is available at www.xilinx.com.

Project IP Instances
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| Instance Name | Status | Recommendation | Change | IP Name | IP | New Version | New | Original Part |
| | | | Log | | Version | | License | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| c_accum_0 | Up-to-date | No changes required | *(1) | Accumulator | 12.0 | 12.0 (Rev. 15) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 15) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_AxiStreamSinkMonitor_0_0 | Up-to-date | No changes required | Change | AxiStreamSinkMonit | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 |
| | | | Log not | | (Rev. | | | |
| | | | available | | 2) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_AxiStreamSourceMonit_0_0 | Up-to-date | No changes required | Change | AxiStreamSourceMon | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 |
| | | | Log not | | (Rev. | | | |
| | | | available | | 2) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_ManualTrigger_0_0 | Up-to-date | No changes required | Change | ManualTrigger | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 |
| | | | Log not | | (Rev. | | | |
| | | | available | | 2) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_TriggerControl_0_0 | Up-to-date | No changes required | Change | TriggerControl | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 |
| | | | Log not | | (Rev. | | | |
| | | | available | | 2) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_UserRegisters_0_0 | Up-to-date | No changes required | Change | UserRegisters | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 |
| | | | Log not | | (Rev. | | | |
| | | | available | | 2) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_ZmodAWGController_0_0 | Up-to-date | No changes required | Change | ZmodAWGController_ | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 |
| | | | Log not | | (Rev. | | | |
| | | | available | | 2) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_ZmodAwgAxiConfigurat_0_0 | Up-to-date | No changes required | Change | ZmodAwgAxiConfigur | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 |
| | | | Log not | | (Rev. | | | |
| | | | available | | 2) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_ZmodScopeAXIConfigur_0_0 | Up-to-date | No changes required | Change | Zmod Scope AXI | 1.0 | 1.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | Log not | Configuration | (Rev. | | | |
| | | | available | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_ZmodScopeController_0_0 | IP contains locked subcore | Upgrade IP or repackage component | Change | ZmodScopeControlle | 1.1 | 1.1 (Rev. 1) | Included | xc7z020clg484-1 |
| | | | Log not | | (Rev. | | | |
| | | | available | | 1) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_axi_dma_0_0 | IP revision change | Upgrade IP | *(2) | AXI Direct Memory | 7.1 | 7.1 (Rev. 29) | Included | xc7z020clg484-1 |
| | | | | Access | (Rev. | | | |
| | | | | | 25) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_axi_dma_0_1 | IP revision change | Upgrade IP | *(3) | AXI Direct Memory | 7.1 | 7.1 (Rev. 29) | Included | xc7z020clg484-1 |
| | | | | Access | (Rev. | | | |
| | | | | | 25) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_axi_fifo_mm_s_0_0 | Up-to-date | No changes required | *(4) | AXI-Stream FIFO | 4.3 | 4.3 | Included | xc7z020clg484-1 |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_axi_lite_rst_0 | Up-to-date | No changes required | *(5) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_axi_lite_rst_1 | Up-to-date | No changes required | *(6) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_axi_lite_rst_2 | Up-to-date | No changes required | *(7) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_axi_reset_0 | Up-to-date | No changes required | *(8) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_axi_rst1_0 | Up-to-date | No changes required | *(9) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_axi_rst_0 | Up-to-date | No changes required | *(10) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_axi_rst_1 | Up-to-date | No changes required | *(11) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_axi_s2mm_rst_0 | Up-to-date | No changes required | *(12) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_axis_clock_converter_0_0 | IP revision change | Upgrade IP | *(13) | AXI4-Stream Clock | 1.1 | 1.1 (Rev. 29) | Included | xc7z020clg484-1 |
| | | | | Converter | (Rev. | | | |
| | | | | | 25) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_axis_clock_converter_0_1 | IP revision change | Upgrade IP | *(14) | AXI4-Stream Clock | 1.1 | 1.1 (Rev. 29) | Included | xc7z020clg484-1 |
| | | | | Converter | (Rev. | | | |
| | | | | | 25) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_axis_clock_converter_0_2 | IP revision change | Upgrade IP | *(15) | AXI4-Stream Clock | 1.1 | 1.1 (Rev. 29) | Included | xc7z020clg484-1 |
| | | | | Converter | (Rev. | | | |
| | | | | | 25) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_axis_clock_converter_0_3 | IP revision change | Upgrade IP | *(16) | AXI4-Stream Clock | 1.1 | 1.1 (Rev. 29) | Included | xc7z020clg484-1 |
| | | | | Converter | (Rev. | | | |
| | | | | | 25) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_axis_mux_0_0 | Up-to-date | No changes required | Change | axis_mux_v1_0 | 1.0 | 1.0 (Rev. 1) | Included | xc7z020clg484-1 |
| | | | Log not | | (Rev. | | | |
| | | | available | | 1) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_axis_register_slice_0_0 | IP revision change | Upgrade IP | *(17) | AXI4-Stream | 1.1 | 1.1 (Rev. 28) | Included | xc7z020clg484-1 |
| | | | | Register Slice | (Rev. | | | |
| | | | | | 24) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_axis_register_slice_0_1 | Up-to-date | No changes required | *(18) | AXI4-Stream | 1.1 | 1.1 (Rev. 28) | Included | xc7z020clg484-1 |
| | | | | Register Slice | (Rev. | | | |
| | | | | | 28) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_c_accum_0_2 | Up-to-date | No changes required | *(19) | Accumulator | 12.0 | 12.0 (Rev. 15) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 15) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_c_accum_1_0 | Up-to-date | No changes required | *(20) | Accumulator | 12.0 | 12.0 (Rev. 15) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 15) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_clk_wiz_0_0 | IP revision change | Upgrade IP | *(21) | Clocking Wizard | 6.0 | 6.0 (Rev. 12) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 8) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_clk_wiz_0_1 | IP revision change | Upgrade IP | *(22) | Clocking Wizard | 6.0 | 6.0 (Rev. 12) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 8) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_create_tlast_0_0 | Up-to-date | No changes required | Change | create_tlast_v1_0 | 1.0 | 1.0 (Rev. 1) | Included | xc7z020clg484-1 |
| | | | Log not | | (Rev. | | | |
| | | | available | | 1) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_extend_pulse_0_0 | Up-to-date | No changes required | Change | extend_pulse_v1_0 | 1.0 | 1.0 (Rev. 1) | Included | xc7z020clg484-1 |
| | | | Log not | | (Rev. | | | |
| | | | available | | 1) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_fclk1_rst1_0 | Up-to-date | No changes required | *(23) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_fclk1_rst2_0 | Up-to-date | No changes required | *(24) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_fclk1_rst_0 | Up-to-date | No changes required | *(25) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_fclk2_rst_0 | Up-to-date | No changes required | *(26) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_ila_0_0 | IP revision change | Upgrade IP | *(27) | ILA (Integrated | 6.2 | 6.2 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Logic Analyzer) | (Rev. | | | |
| | | | | | 11) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_inject_tlast_on_trig_0_0 | Up-to-date | No changes required | Change | inject_tlast_on_tr | 1.0 | 1.0 (Rev. 1) | Included | xc7z020clg484-1 |
| | | | Log not | | (Rev. | | | |
| | | | available | | 1) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_level_trigger_0_0 | Up-to-date | No changes required | Change | level_trigger_v1_0 | 1.0 | 1.0 (Rev. 1) | Included | xc7z020clg484-1 |
| | | | Log not | | (Rev. | | | |
| | | | available | | 1) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_mm2s_rst_0 | Up-to-date | No changes required | *(28) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_processing_system7_0_0 | Up-to-date | No changes required | *(29) | ZYNQ7 Processing | 5.5 | 5.5 (Rev. 6) | Included | xc7z020clg484-1 |
| | | | | System | (Rev. | | | |
| | | | | | 6) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_ps7_0_axi_periph_gp0_0 | IP revision change | Upgrade IP | *(30) | AXI Interconnect | 2.1 | 2.1 (Rev. 29) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 25) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_resolution_0 | Up-to-date | No changes required | *(31) | Slice | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 2) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_sg_rst1_0 | Up-to-date | No changes required | *(32) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_sg_rst2_0 | Up-to-date | No changes required | *(33) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_sg_rst3_0 | Up-to-date | No changes required | *(34) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_sg_rst4_0 | Up-to-date | No changes required | *(35) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_sg_rst_0 | Up-to-date | No changes required | *(36) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_smartconnect_0_0 | IP revision change. IP contains locked subcore | Upgrade IP | *(37) | AXI SmartConnect | 1.0 | 1.0 (Rev. 20) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_smartconnect_1_0 | IP revision change. IP contains locked subcore | Upgrade IP | *(38) | AXI SmartConnect | 1.0 | 1.0 (Rev. 20) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_smartconnect_2_0 | IP revision change. IP contains locked subcore | Upgrade IP | *(39) | AXI SmartConnect | 1.0 | 1.0 (Rev. 20) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 16) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_stream_rst_0 | Up-to-date | No changes required | *(40) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_stream_rst_1 | Up-to-date | No changes required | *(41) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_stream_rst_2 | Up-to-date | No changes required | *(42) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_stream_rst_3 | Up-to-date | No changes required | *(43) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_stream_rst_4 | Up-to-date | No changes required | *(44) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_system_ila_0_0 | IP revision change. IP contains locked subcore | Upgrade IP | *(45) | System ILA | 1.1 | 1.1 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 10) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_system_ila_1_0 | IP revision change. IP contains locked subcore | Upgrade IP | *(46) | System ILA | 1.1 | 1.1 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 10) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_test_stream_sink_0_0 | Up-to-date | No changes required | Change | test_stream_sink_v | 1.0 | 1.0 (Rev. 1) | Included | xc7z020clg484-1 |
| | | | Log not | | (Rev. | | | |
| | | | available | | 1) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_traffic_generator_0_0 | Up-to-date | No changes required | Change | traffic_generator_ | 1.0 | 1.0 (Rev. 1) | Included | xc7z020clg484-1 |
| | | | Log not | | (Rev. | | | |
| | | | available | | 1) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_xlconcat_0_0 | Up-to-date | No changes required | *(47) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 4) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_xlconcat_0_1 | Up-to-date | No changes required | *(48) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 4) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_xlconcat_1_0 | Up-to-date | No changes required | *(49) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 4) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_xlslice_0_0 | Up-to-date | No changes required | *(50) | Slice | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 2) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_xlslice_15_downto_0_1 | Up-to-date | No changes required | *(51) | Slice | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 2) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_xlslice_1_0 | Up-to-date | No changes required | *(52) | Slice | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 2) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| design_1_xlslice_31_downto_16_1 | Up-to-date | No changes required | *(53) | Slice | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 2) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| ZmodADC_SynchonizationFIFO | IP revision change | Upgrade parent IP | *(54) | FIFO Generator | 13.2 | 13.2 (Rev. 8) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 5) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_365d_g_inst_0 | Incompatible IP data detected | Repackage parent IP | Change | Gigantic mux | 1.0 | 1.0 (Rev. 1) | Included | xc7z020clg484-1 |
| | | | Log not | | (Rev. | | | |
| | | | available | | 1) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_365d_ila_lib_0 | IP revision change | Repackage parent IP | *(55) | ILA (Integrated | 6.2 | 6.2 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Logic Analyzer) | (Rev. | | | |
| | | | | | 11) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_arsw_0 | Up-to-date | No changes required | *(56) | SmartConnect | 1.0 | 1.0 (Rev. 6) | Included | xc7z020clg484-1 |
| | | | | Switchboard | (Rev. | | | |
| | | | | | 6) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_awsw_0 | Up-to-date | No changes required | *(57) | SmartConnect | 1.0 | 1.0 (Rev. 6) | Included | xc7z020clg484-1 |
| | | | | Switchboard | (Rev. | | | |
| | | | | | 6) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_bsw_0 | Up-to-date | No changes required | *(58) | SmartConnect | 1.0 | 1.0 (Rev. 6) | Included | xc7z020clg484-1 |
| | | | | Switchboard | (Rev. | | | |
| | | | | | 6) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_m00arn_0 | IP revision change | Repackage parent IP | *(59) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_m00awn_0 | IP revision change | Repackage parent IP | *(60) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_m00bn_0 | IP revision change | Repackage parent IP | *(61) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_m00e_0 | IP revision change | Repackage parent IP | *(62) | SC EXIT | 1.0 | 1.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 11) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_m00rn_0 | IP revision change | Repackage parent IP | *(63) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_m00s2a_0 | IP revision change | Repackage parent IP | *(64) | SmartConnect | 1.0 | 1.0 (Rev. 8) | Included | xc7z020clg484-1 |
| | | | | SC2AXI Bridge | (Rev. | | | |
| | | | | | 7) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_m00wn_0 | IP revision change | Repackage parent IP | *(65) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_one_0 | Incompatible IP data detected | Repackage parent IP | *(66) | Constant | 1.1 | 1.1 (Rev. 7) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 7) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_psr_aclk_0 | Up-to-date | No changes required | *(67) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_rsw_0 | Up-to-date | No changes required | *(68) | SmartConnect | 1.0 | 1.0 (Rev. 6) | Included | xc7z020clg484-1 |
| | | | | Switchboard | (Rev. | | | |
| | | | | | 6) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_s00a2s_0 | IP revision change | Repackage parent IP | *(69) | SmartConnect | 1.0 | 1.0 (Rev. 8) | Included | xc7z020clg484-1 |
| | | | | AXI2SC Bridge | (Rev. | | | |
| | | | | | 7) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_s00mmu_0 | IP revision change | Repackage parent IP | *(70) | SC MMU | 1.0 | 1.0 (Rev. 11) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 10) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_s00sic_0 | IP revision change | Repackage parent IP | *(71) | SC SI_CONVERTER | 1.0 | 1.0 (Rev. 11) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 10) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_s00tr_0 | Up-to-date | No changes required | *(72) | SC | 1.0 | 1.0 (Rev. 9) | Included | xc7z020clg484-1 |
| | | | | TRANSACTION_REGULA | (Rev. | | | |
| | | | | | 9) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_s01a2s_0 | IP revision change | Repackage parent IP | *(73) | SmartConnect | 1.0 | 1.0 (Rev. 8) | Included | xc7z020clg484-1 |
| | | | | AXI2SC Bridge | (Rev. | | | |
| | | | | | 7) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_s01mmu_0 | IP revision change | Repackage parent IP | *(74) | SC MMU | 1.0 | 1.0 (Rev. 11) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 10) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_s01sic_0 | IP revision change | Repackage parent IP | *(75) | SC SI_CONVERTER | 1.0 | 1.0 (Rev. 11) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 10) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_s01tr_0 | Up-to-date | No changes required | *(76) | SC | 1.0 | 1.0 (Rev. 9) | Included | xc7z020clg484-1 |
| | | | | TRANSACTION_REGULA | (Rev. | | | |
| | | | | | 9) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_sarn_0 | IP revision change | Repackage parent IP | *(77) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_sarn_1 | IP revision change | Repackage parent IP | *(78) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_sawn_0 | IP revision change | Repackage parent IP | *(79) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_sawn_1 | IP revision change | Repackage parent IP | *(80) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_sbn_0 | IP revision change | Repackage parent IP | *(81) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_sbn_1 | IP revision change | Repackage parent IP | *(82) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_srn_0 | IP revision change | Repackage parent IP | *(83) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_srn_1 | IP revision change | Repackage parent IP | *(84) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_swn_0 | IP revision change | Repackage parent IP | *(85) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_swn_1 | IP revision change | Repackage parent IP | *(86) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_48ac_wsw_0 | Up-to-date | No changes required | *(87) | SmartConnect | 1.0 | 1.0 (Rev. 6) | Included | xc7z020clg484-1 |
| | | | | Switchboard | (Rev. | | | |
| | | | | | 6) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_880d_m00e_0 | IP revision change | Repackage parent IP | *(88) | SC EXIT | 1.0 | 1.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 11) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_880d_m00s2a_0 | IP revision change | Repackage parent IP | *(89) | SmartConnect | 1.0 | 1.0 (Rev. 8) | Included | xc7z020clg484-1 |
| | | | | SC2AXI Bridge | (Rev. | | | |
| | | | | | 7) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_880d_one_0 | Incompatible IP data detected | Repackage parent IP | *(90) | Constant | 1.1 | 1.1 (Rev. 7) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 7) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_880d_psr_aclk_0 | Up-to-date | No changes required | *(91) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_880d_s00a2s_0 | IP revision change | Repackage parent IP | *(92) | SmartConnect | 1.0 | 1.0 (Rev. 8) | Included | xc7z020clg484-1 |
| | | | | AXI2SC Bridge | (Rev. | | | |
| | | | | | 7) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_880d_s00mmu_0 | IP revision change | Repackage parent IP | *(93) | SC MMU | 1.0 | 1.0 (Rev. 11) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 10) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_880d_s00sic_0 | IP revision change | Repackage parent IP | *(94) | SC SI_CONVERTER | 1.0 | 1.0 (Rev. 11) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 10) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_880d_s00tr_0 | Up-to-date | No changes required | *(95) | SC | 1.0 | 1.0 (Rev. 9) | Included | xc7z020clg484-1 |
| | | | | TRANSACTION_REGULA | (Rev. | | | |
| | | | | | 9) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_880d_sarn_0 | IP revision change | Repackage parent IP | *(96) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_880d_srn_0 | IP revision change | Repackage parent IP | *(97) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_88fd_m00e_0 | IP revision change | Repackage parent IP | *(98) | SC EXIT | 1.0 | 1.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 11) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_88fd_m00s2a_0 | IP revision change | Repackage parent IP | *(99) | SmartConnect | 1.0 | 1.0 (Rev. 8) | Included | xc7z020clg484-1 |
| | | | | SC2AXI Bridge | (Rev. | | | |
| | | | | | 7) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_88fd_one_0 | Incompatible IP data detected | Repackage parent IP | *(100) | Constant | 1.1 | 1.1 (Rev. 7) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 7) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_88fd_psr_aclk_0 | Up-to-date | No changes required | *(101) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Reset | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_88fd_s00a2s_0 | IP revision change | Repackage parent IP | *(102) | SmartConnect | 1.0 | 1.0 (Rev. 8) | Included | xc7z020clg484-1 |
| | | | | AXI2SC Bridge | (Rev. | | | |
| | | | | | 7) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_88fd_s00mmu_0 | IP revision change | Repackage parent IP | *(103) | SC MMU | 1.0 | 1.0 (Rev. 11) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 10) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_88fd_s00sic_0 | IP revision change | Repackage parent IP | *(104) | SC SI_CONVERTER | 1.0 | 1.0 (Rev. 11) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 10) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_88fd_s00tr_0 | Up-to-date | No changes required | *(105) | SC | 1.0 | 1.0 (Rev. 9) | Included | xc7z020clg484-1 |
| | | | | TRANSACTION_REGULA | (Rev. | | | |
| | | | | | 9) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_88fd_sawn_0 | IP revision change | Repackage parent IP | *(106) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_88fd_sbn_0 | IP revision change | Repackage parent IP | *(107) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_88fd_swn_0 | IP revision change | Repackage parent IP | *(108) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 13) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_f60c_g_inst_0 | Incompatible IP data detected | Repackage parent IP | Change | Gigantic mux | 1.0 | 1.0 (Rev. 1) | Included | xc7z020clg484-1 |
| | | | Log not | | (Rev. | | | |
| | | | available | | 1) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_f60c_ila_lib_0 | IP revision change | Repackage parent IP | *(109) | ILA (Integrated | 6.2 | 6.2 (Rev. 13) | Included | xc7z020clg484-1 |
| | | | | Logic Analyzer) | (Rev. | | | |
| | | | | | 11) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_f60c_slot_0_ar_0 | Up-to-date | No changes required | *(110) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 4) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_f60c_slot_0_aw_0 | Up-to-date | No changes required | *(111) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 4) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_f60c_slot_0_b_0 | Up-to-date | No changes required | *(112) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 4) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_f60c_slot_0_r_0 | Up-to-date | No changes required | *(113) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 4) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_f60c_slot_0_w_0 | Up-to-date | No changes required | *(114) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 4) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_f60c_slot_1_ar_0 | Up-to-date | No changes required | *(115) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 4) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_f60c_slot_1_aw_0 | Up-to-date | No changes required | *(116) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 4) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_f60c_slot_1_b_0 | Up-to-date | No changes required | *(117) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 4) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_f60c_slot_1_r_0 | Up-to-date | No changes required | *(118) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 4) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_f60c_slot_1_w_0 | Up-to-date | No changes required | *(119) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 4) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_f60c_slot_2_ar_0 | Up-to-date | No changes required | *(120) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 4) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_f60c_slot_2_aw_0 | Up-to-date | No changes required | *(121) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 4) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_f60c_slot_2_b_0 | Up-to-date | No changes required | *(122) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 4) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_f60c_slot_2_r_0 | Up-to-date | No changes required | *(123) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 4) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
| bd_f60c_slot_2_w_0 | Up-to-date | No changes required | *(124) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 |
| | | | | | (Rev. | | | |
| | | | | | 4) | | | |
+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+
*(1) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/c_accum_v12_0/doc/c_accum_v12_0_changelog.txt
*(2) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/axi_dma_v7_1/doc/axi_dma_v7_1_changelog.txt
*(3) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/axi_dma_v7_1/doc/axi_dma_v7_1_changelog.txt
*(4) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/axi_fifo_mm_s_v4_3/doc/axi_fifo_mm_s_v4_3_changelog.txt
*(5) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt
*(6) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt
*(7) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt
*(8) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt
*(9) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt
*(10) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt
*(11) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt
*(12) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt
*(13) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/axis_clock_converter_v1_1/doc/axis_clock_converter_v1_1_changelog.txt
*(14) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/axis_clock_converter_v1_1/doc/axis_clock_converter_v1_1_changelog.txt
*(15) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/axis_clock_converter_v1_1/doc/axis_clock_converter_v1_1_changelog.txt
*(16) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/axis_clock_converter_v1_1/doc/axis_clock_converter_v1_1_changelog.txt
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Xband · December 27, 2023

This is getting worse, now it doesn't see the "design_1" wrapper file....

saw something about if you move between simulation and design it places things in an "imports" folder that can cause issues, though I don't see a solution for this issue.

C:/Users/LENOVO/Documents/GitHub/hw/hw.srcs/sources_1/imports/hdl/design_1_wrapper.v

Edited December 27, 2023 by Xband

zygot · December 27, 2023

Gee, I've been following this thread since it started.. two months ago.
This one took me less than 2 week effort: https://forum.digilent.com/topic/20153-capture-4-channels-of-120-million-adc-samples/

Guess which platform I think of as "rapid development" and which one I think of as a sinkhole for time and effort ( not that one can't learn an awful lot about stuff that isn't necessary to implement very useful projects. You've probably heard of K.I.S.S.; how about ITPS ( It's The Platform Silly )

Projects for collecting large mounts of data and moving it to a PC are so much easier without Vitis, ZYNQ, Vivado IP.. just an HDL and one software application in C.

But everyone hast the right to pick their own poison I suppose. Edited December 27, 2023 by zygot

Xband · December 28, 2023

Thanks, that's helpful. I've been at this sporadically while taking care of a family member who has been in and out of the hospital. Again I don't see it as a problem with the hardware, Vivado is a mess and non intuitive, I'm using the proper platform for my application .

I"ve been cordial with your drop in remarks, I suggest you unfollow the conversation if you don't have anything to contribute.

Edited December 28, 2023 by Xband

zygot · December 28, 2023

Stop with the commentary that you find to be not at all helpful. So noted...

I apologize if my comments seems snide; they aren't at all, I just hate to see someone struggle unnecessarily.

I agree that Vivado is buggy and difficult to get along with. But it still understands VHDL, Verilog and System Verilog. My theory is that the more control that a developer has, the easier the overall effort in the long run. That opinion is based on experience using tools from all of the FPGA vendors. With ZYNQ you need to use AXI bus structures, and you need to accommodate all of the ARM peculiarities. That's more complications. An you can't simulate a whole design.

You like the Eclipse-Z7 hardware. Good for you. Keep on keeping on, as they say.

In the future I'll force myself not to read this thread. No more comments.

The project that I linked to above was also done in my spare time as an exercise of curiosity. No frustration at all. Edited December 28, 2023 by zygot

Xband · December 28, 2023

@zygot yeah I had the main project working quickly also, its the modifications that cause problems and the accompanying gaps in the workflow in Vivado that come along. I search Xilinx forums each time before reposting here and find people encountering the exact problems I am having years ago and there are not clear solutions to the same annoyance I'm having.

Part of my problem could be I'm using 2023.1 and the original project is in 20xx.x, I don't know. At some point I might download the same version and go through it.

The current stumbling block is that Vivado changed the directory for ip from the baseline to a "temporary" and seemed to forget it does this for some reason. So I as a novice need to figure out what trick I can pull to make it ok. Maybe rebuilding the project in an earlier version is the best solution at this point, I don't know.

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