Ethernet PHY in Arty Z7-20

[albugo]

Hi,

I am a beginner in FPGA. I am trying to make a counter for digital pulses with its time tagged data(Arty Z7-20 board, 100 MBps data transfer expected). For a start I have made a simple frequency counter HDL code which counts the pulses from signal.
Now I want to send the frequency_out data to PC via ethernet PHY. I understand that I need to connect my PL to PS and make a software and server. But really can't understand how to? Can anyone recommend good recourses that can guide me to accomplish this.

I have attached below the VHDL code which works fine. I have tried to make a block design. 

[artvvb]

For a start on ethernet, check out this guide for using TCP with Zynq: https://digilent.com/reference/programmable-logic/guides/zynq-servers. That said, 100 MBps is likely too much data for this setup, I'm not certain. In addition to the LwIP example, Xilinx also provides some examples for checking performance.

AXI ethernet is not required - it's for interfacing with PHYs that are connected to the PL, whereas the Arty Z7 makes use of the PS ethernet controller, which is enabled by default in the Zynq config.

As for interfacing between PL and PS, there are many ways of going about it, depending on throughput requirements. Connecting the IOs of an RTL module to Zynq EMIO pins or an AXI GPIO would be an easy first step, but both have significant data throughput limitations. Creating an AXI interface for the frequency counter is an option, but would be a lot for a beginner. Putting data into an AXI stream interface which forwards data to DDR via an AXI DMA would be the most straightforward solution if you need to move a lot of data, or move data nearly every clock cycle, but again, there's quite a bit involved - DMA audio demos for other Zynq boards, like this one, might be a decent starting point, but would still require quite a bit of learning to implement.

Thanks,

Arthur