What VHDL code is needed to operate the XADC after configuring the wizard

[oldViking]

Hi, 

I am trying to operate the XADC on my Arty S7.  I think I have the wizard set up to operate in a continuous mode.

When the wizard is open, it shows a pinout of the module.  Two of the inputs are the dclk_in, and the reset_in.

Is it my responsibility to add VHDL code that will connect these pins to the correct signal ?

If so do you have some sample VHDL code that will provide some guidance ?  I have no idea where to get a reset signal from.

As a first step, before looking at conversion data, I would be satisfied to see the output signal eoc_out changing states in a predictable manner (on my scope).

Thank you

oldViking

[artvvb]

Hi @oldViking

Yes, providing clocks, resets, and some logic to control the XADC DRP interface is required from the user. Digilent doesn't provide VHDL for it, but you can see equivalent Verilog in this demo: https://digilent.com/reference/programmable-logic/arty-s7/demos/xadc. The source for the top module is here: https://github.com/Digilent/Arty-S7-HW/blob/9904101ccd8f35003e4a6760a2d500f814d21b73/src/hdl/XADCdemo.v. In the case of this demo the reset is tied low.

Thanks,

Arthur