TIMING #1 The clocks DcoClk_1 and DcoClk_0 are related (timed together) but they have no common primary clock.

[Xband]

Greetings, 

this problem is probably obvious to the trained eye, my project consists of 2 Zmod1410 ADC's in the project, trying to generate the 4 channels of data to manipulate in the SOC at some point.  Project is based on the Knitter examples in hackster, finally have the constraints working I think and now having clock issues.   Three similar errors.  

The clocks DcoClk_1 and DcoClk_0 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks DcoClk_1] -to [get_clocks DcoClk_0]

TIMING #2 The clocks clk_fpga_0 and clk_fpga_1 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_fpga_0] -to [get_clocks clk_fpga_1] 

TIMING #3 The clocks clk_fpga_1 and clk_fpga_0 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_fpga_1] -to [get_clocks clk_fpga_0] 

Common mode errors accompany these;

TIMING #1 The clocks DcoClk_1 and DcoClk_0 are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks DcoClk_1] -to [get_clocks DcoClk_0] 

 

Anything else to post to help figure this out.  

 

Thanks for any help. 

 

 

 

report_timing -from [get_clocks DcoClk_1] -to [get_clocks DcoClk_0]
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-78] ReportTimingParams: -from_pins  -to_pins  -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
WARNING: [Timing 38-164] This design has multiple clocks. Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
| Date         : Tue Sep 12 15:54:22 2023
| Host         : JIMT16 running 64-bit major release  (build 9200)
| Command      : report_timing -from [get_clocks DcoClk_1] -to [get_clocks DcoClk_0]
| Design       : design_1_wrapper
| Device       : 7z020-clg484
| Speed File   : -1  PRODUCTION 1.12 2019-11-22
| Design State : Routed
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Timing Report

Slack (MET) :             0.051ns  (required time - arrival time)
  Source:                 dADC_Data_0[11]
                            (input port clocked by DcoClk_1  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            design_1_i/ZmodADC1410_Controll_1/U0/GenerateIDDR[11].InstIDDR/D
                            (rising edge-triggered cell IDDR clocked by DcoClk_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             DcoClk_0
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            5.000ns  (DcoClk_0 fall@5.000ns - DcoClk_1 rise@0.000ns)
  Data Path Delay:        0.375ns  (logic 0.375ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Input Delay:            5.440ns
  Clock Path Skew:        0.904ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.904ns = ( 5.904 - 5.000 ) 
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock DcoClk_1 rise edge)
                                                      0.000     0.000 r  
                         input delay                  5.440     5.440    
    J22                                               0.000     5.440 r  dADC_Data_0[11] (IN)
                         net (fo=0)                   0.000     5.440    dADC_Data_0[11]
    J22                  IBUF (Prop_ibuf_I_O)         0.375     5.815 r  dADC_Data_0_IBUF[11]_inst/O
                         net (fo=1, routed)           0.000     5.815    design_1_i/ZmodADC1410_Controll_1/U0/dADC_Data[11]
    ILOGIC_X1Y83         IDDR                                         r  design_1_i/ZmodADC1410_Controll_1/U0/GenerateIDDR[11].InstIDDR/D
  -------------------------------------------------------------------    -------------------

                         (clock DcoClk_0 fall edge)
                                                      5.000     5.000 f  
    M19                                               0.000     5.000 f  DcoClk_0 (IN)
                         net (fo=0)                   0.000     5.000    DcoClk_0
    M19                  IBUF (Prop_ibuf_I_O)         0.151     5.151 f  DcoClk_0_IBUF_inst/O
                         net (fo=2, routed)           0.179     5.330    design_1_i/ZmodADC1410_Controll_1/U0/DcoClk
    BUFIO_X1Y5           BUFIO (Prop_bufio_I_O)       0.483     5.813 f  design_1_i/ZmodADC1410_Controll_1/U0/InstDcoBufio/O
                         net (fo=14, routed)          0.091     5.904    design_1_i/ZmodADC1410_Controll_1/U0/DcoBufioClk
    ILOGIC_X1Y83         IDDR                                         f  design_1_i/ZmodADC1410_Controll_1/U0/GenerateIDDR[11].InstIDDR/C
                         clock pessimism              0.000     5.904    
                         clock uncertainty           -0.035     5.868    
    ILOGIC_X1Y83         IDDR (Setup_iddr_C_D)       -0.002     5.866    design_1_i/ZmodADC1410_Controll_1/U0/GenerateIDDR[11].InstIDDR
  -------------------------------------------------------------------
                         required time                          5.866    
                         arrival time                          -5.815    
  -------------------------------------------------------------------
                         slack                                  0.051  

[artvvb]

This is a pretty sketchy error - unintended clock domain crossings and missing location constraints. If you'd like help with issue, please provide additional information on the clocking scheme for your Zmods. Otherwise, I'm looking forward to hearing if the ILA design provided in another thread works for you.

Thanks,

Arthur

[Xband]

@artvvb

I have the hardware design loaded and a software SOC testing now.  Exciting progress!  Getting an XAXIDMA_Device_To_DMA transfer length failure now!  Progress!

Thanks for your continuing support, sorry to have two separate threads on my issues going.

[Xband]

@artvvb,

I should take this on another thread possibly.  I'm reading the AD9648 documents and it is saying that the DCO clocks are used for eternal triggering of the ADC.  In a perfect world my application will possibly sent a trigger in through a Pmode channel to initiate the acquisition.  I say Pmod because it seems to me to be the existing DIO for the Eclypse board.  

I've gotten through the above errors and have another query about a function that is causing an error in the Vitus build.  "adcZmod()"  seems to pop up in multiple places but I cannot determine where it is defined, or where to link to it.