Zybo Z7: Wrong PLL settings?

[Michael Fischer]

Hello Digilent Support Team,

I think there are wrong settings in the board files for Zybo Z7 10 and 20.

Here the APU frequency should be 667MHz, but therefore the ARMPLL_CTRL_FBDIV
was wrong with 39. With 39 and a crystal of 33.33MHz, this produce a PLL frequency of
33.333MHz x 39 = 1300MHz, but with a CPU divisor of 2, this will result in a CPU frequency of
650MHz and not 667MHz.

Please take a look at the PR I have created:
https://github.com/Digilent/vivado-boards/pull/44

Best regards,
Michael

[artvvb]

Hi Michael,

Thanks for the PR, we're looking into it, and I will update here once we've had a chance to review.

-Arthur

[artvvb]

Merged in, thanks!

-Arthur