Pixels per clock change in MIPI CSI RX

[RisingPheonix]

Hello,

I wish to know whether anyone has tried to change the pixels per clock value set in the MIPI CSI2 RX module present in the Digilent vivado library given here. I tried editing that code to set it to 1 pixel per clock and TDATA width to 10, but the IP doesn't get synthesized in Vivado.

Edited July 31, 2023 by RisingPheonix
Added screenshots

[Ionut]

Hi @RisingPheonix,

 

The MIPI_CSI2_Rx.vhd file you are referencing in your post is not the toplevel file of that IP. The toplevel is MIPI_CSI2_RxTop.vhd (linked here). Furthermore, the CSI2 RX is packaged as a Vivado IP, meaning it has a configuration GUI where you can change the settings you mentioned (please see the image below):

• Pixel Format - RAW8, RAW10 etc.;
• Pixels per Clock - 1, 2 or 4.

To view this configuration GUI and edit its settings, you need to first create a block design in Vivado (if you do not have one already in your project), add this IP to the block design and then double click on the IP. After you change the settings, click "OK", connect the IP in the block design, save the block design, then press the "Validate Design" button in the upper part of the block design and the IP port widths will then be automatically updated to match your new settings.

Could you try this approach to customize the IP and let me know if you encounter any issues?

 

Best Regards,

Ioan.