Zmod Scope Controller 1.0 IP Core User Guide (Revised September 9, 2021; Author Tudor Gherman)

[uFedor]

Dear Support!

Question:

Please explain why ZmodDcoClk signal in the Table 12. "IP core port description" is defined as input, but in the Figure 1. "Zmod Scope Controller block diagram" it is internally connected already?

The question corresponds to the IP representation (and connection) in the Vivado 2022.2 - refer to the attached screenshot.

[artvvb]

Hi @uFedor

In Figure 1, everything within the "Zmod Scope" box is external to the FPGA, while the "Zmod Scope Controller" box is IP internal to the FPGA - lines running between these boxes are all routed through FPGA pins and the SYZYGY connector. The FPGA treats the Zmod DcoClk as an input, which also needs to be constrained to appropriate pin locations for whichever physical Zmod port the instantiated controller is to be connected to.

Thanks,

Arthur

[uFedor]

Thank you for the response.

How in this case the ZmodDcoClk has to be connected in the block diagram?

[artvvb]

It should be an input to the block design, an external port:

[uFedor]

Thank you for the answer.

Edited July 20, 2023 by uFedor