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uFedor

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  1. Thank you for the response. How in this case the ZmodDcoClk has to be connected in the block diagram?
  2. Dear Support! Question: Please explain why ZmodDcoClk signal in the Table 12. "IP core port description" is defined as input, but in the Figure 1. "Zmod Scope Controller block diagram" it is internally connected already? The question corresponds to the IP representation (and connection) in the Vivado 2022.2 - refer to the attached screenshot.
  3. Hello! On the webpage (https://digilent.com/reference/learn/programmable-logic/tutorials/vivado-hierarchical-blocks/start) it is described how to use vivado-library vivado-library-zmod-v1-2019.1-2.zip containing: AXI_Zmod_ADC1410 AXI_Zmod_DAC1411 ZmodADC1410Controller ZmodDAC1411_Controller Modern vivado-library GIT contains only: ZmodAWGController ZmodDigitizerController Where is usage description for the modern IPs? Regards, Fedor Baev
  4. Hello! On the webpage (https://digilent.com/reference/learn/programmable-logic/tutorials/vivado-hierarchical-blocks/start) it is described how to use vivado-library vivado-library-zmod-v1-2019.1-2.zip containing: AXI_Zmod_ADC1410 AXI_Zmod_DAC1411 ZmodADC1410Controller ZmodDAC1411_Controller Modern vivado-library GIT contains only: ZmodAWGController ZmodDigitizerController Where is usage description for the modern IPs? Regards, Fedor Baev
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