Hello, I am currently working on synthesizing an open-source CPU based on the RISC-V architecture called NeoRV32. My goal is to be able to debug it using a JTAG interface. After successfully synthesizing and implementing it in VIVADO, the final step is to generate the bitstream.
I have noticed in the datasheet and on the board itself that a JTAG port is present. However, when I enter the names of the pins provided in the electronic schematic, VIVADO does not recognize them. Additionally, I have checked the constraint file [https://github.com/Digilent/Nexys-A7-100T-Keyboard/blob/master/src/constraints/Nexys-A7-100T-Master.xdc ], and it seems that these pins are not present there either.
I would like to gather more information about these peripherals and understand why VIVADO does not recognize them. If you could provide any insights or guidance on how to properly include these pins in the constraint file, I would greatly appreciate it.
Question
cmenende
Hello, I am currently working on synthesizing an open-source CPU based on the RISC-V architecture called NeoRV32. My goal is to be able to debug it using a JTAG interface. After successfully synthesizing and implementing it in VIVADO, the final step is to generate the bitstream.
I have noticed in the datasheet and on the board itself that a JTAG port is present. However, when I enter the names of the pins provided in the electronic schematic, VIVADO does not recognize them. Additionally, I have checked the constraint file [https://github.com/Digilent/Nexys-A7-100T-Keyboard/blob/master/src/constraints/Nexys-A7-100T-Master.xdc ], and it seems that these pins are not present there either.
I would like to gather more information about these peripherals and understand why VIVADO does not recognize them. If you could provide any insights or guidance on how to properly include these pins in the constraint file, I would greatly appreciate it.
Thank you in advance for your assistance
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