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JTAG connexion on a NEXYS A7 100t BOARD


cmenende

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Hello, I am currently working on synthesizing an open-source CPU based on the RISC-V architecture called NeoRV32. My goal is to be able to debug it using a JTAG interface. After successfully synthesizing and implementing it in VIVADO, the final step is to generate the bitstream.

I have noticed in the datasheet and on the board itself that a JTAG port is present. However, when I enter the names of the pins provided in the electronic schematic, VIVADO does not recognize them. Additionally, I have checked the constraint file [https://github.com/Digilent/Nexys-A7-100T-Keyboard/blob/master/src/constraints/Nexys-A7-100T-Master.xdc ], and it seems that these pins are not present there either.

I would like to gather more information about these peripherals and understand why VIVADO does not recognize them. If you could provide any insights or guidance on how to properly include these pins in the constraint file, I would greatly appreciate it.

Thank you in advance for your assistance

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Vivado readily connects to Digilent and Xilinx JTAG programming hardware. You'll want this if using the ILA or VIO debugging cores.

All Digilent boards have a PROG USB header using a USB bridge device from FTDI or Cypress. You OS needs to recognize USB devices as for a specific use. Using the USB connector on a Digilent board that supports JTAG is the easiest way to configure your FPGA.

You can use OpenOCD with a bit of work, but what would drive the need to do so?

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Hi @cmenende

JTAG pins are located at fixed locations on the FPGA part and do not need to be constrained. BSCAN primitives instantiated in your design can be used to access them after bitstream programming - ILAs and the microblaze debug module do this, for example. However, I'm not sure what the software requirements would be to be able to debug your specific cores. This repo seems to indicate it's possible: https://github.com/eugene-tarassov/vivado-risc-v

Thanks,

Arthur

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