NEXYS A7 JTAG CONNEXION

[cmenende]

I am writing to discuss a technical issue I have encountered while working on a project in the NEXYS A7 100t board. Specifically, I am facing difficulties in establishing a connection with the JTAG interface.

Due to the fact that J10 ports are not being recognized by Vivado, I have resorted to using a PMOD to extract the signals for JTAG. I have connected the JTAG HS2 and modified the OpenOCD configuration file accordingly. However, I am currently unable to establish a successful connection.

I have thoroughly reviewed my setup and configuration to ensure that all connections and settings are correct. Despite my efforts, I have been unable to resolve the connectivity issue. I have also consulted relevant documentation and online resources, but the problem persists.

Here you can see the error  and the configuration files.

Thank you in advance for your time.

[zygot]

Connecting to a JTAG chain isn't as straight-forward as you might assume.

I suggest trying to resolve your connection issues using the normal Digilent means.

What is your host OS?

 

[cmenende]

I tried to but the problem is that the pins of the J10 port specified in the datasheet and schematics are not in the constraint file provided by diligent ( here you can see the constraint file I am using : https://github.com/Digilent/Nexys-A7-100T-Keyboard/blob/master/src/constraints/Nexys-A7-100T-Master.xdc ) . and even if I write the pins names provided in the schematics they are not recognized by VIVADO. 

I am using VIVADO in windows and for the GDB, OpenOCD Ubuntu

[zygot]

J6 is the USB connector for FPGA configuration. If you connect a cable to J6 Vivado should see a Digilent device and connect to it.

J10 is an alternate way to use the board's JTAG chain. In this case you need a separate USB JTAG controller that Vivado will recognize, like  Digilent HS3 or Xilinx cable. Usually, the open JTAG header ( not a USB connection ) is a 14-pin keyed connector. You can't use both at the same time.

J10 pins are not provided in the master constraints file because they are generally not used as general purpose IO.

Have you reviewed the board's reference manual?

 

[cmenende]

5 minutes ago, zygot said:

J6 is the USB connector for FPGA configuration. If you connect a cable to J6 Vivado should see a Digilent device and connect to it.

J10 is an alternate way to use the board's JTAG chain. In this case you need a separate USB JTAG controller that Vivado will recognize, like  Digilent HS3 or Xilinx cable. Usually, the open JTAG header ( not a USB connection ) is a 14-pin keyed connector. You can't use both at the same time.

J10 pins are not provided in the master constraints file because they are generally not used as general purpose IO.

Have you reviewed the board's reference manual?

 

I actually have the Diligent HS2 ( sorry I forgot to mention that). That's why I am trying to connect it to the J10 port.

 

[zygot]

More than likely, you will have to figure out how to connect your HS2 to J10. I have an older Digilent USB JTAG cable for use with the old 6-pin header; I imagine that this would work on J10 of your board.

Regrettably, Digilent refuses to provide schematics for it's configuration related functionality. Perhaps you don't want to be using a Digilent FPGA board for your project.

What utility do you expect to get by using J10 instead of the normal J6 JTAG connectivity?

[cmenende]

I would like to use my HS2 because I need to use a ftdi in order to connect it to OpenOCD and then be able to debug with GDB.

But what is the point of having a J10 port if you don't provide the pins' names add them to the contraint file and make it work?!

[cmenende]

8 minutes ago, zygot said:

More than likely, you will have to figure out how to connect your HS2 to J10. I have an older Digilent USB JTAG cable for use with the old 6-pin header; I imagine that this would work on J10 of your board.

Regrettably, Digilent refuses to provide schematics for it's configuration related functionality. Perhaps you don't want to be using a Digilent FPGA board for your project.

What utility do you expect to get by using J10 instead of the normal J6 JTAG connectivity?

But I don't need the schematics if the constraint file is complete. 

It is frustrating....

What is the point to sell a JTAG HS connector if you can't connect it to the board because they don't provide more information?

[zygot]

All of the Series 7 FPGA boards from Digilent use an FTDI USB bridge device for configuration and as a UART. I figure that you would just configure your FPGA and use GDB using J6. As I mentioned, you can cannot connect 2 external USB JTAG devices to your board.

Edited July 5, 2023 by zygot

[zygot]

19 minutes ago, cmenende said:

But I don't need the schematics if the constraint file is complete. 

I think that you have that backwards; you don't need pin locations unless you intend to use the configuration specific pins as general purpose IO post configuration. For a general purpose board like Digilent sells I don't know of any application that needs to do this. The constraint files are for assigning IO to your FPGA HW application. You don't need this information ( usually ) for configuration. Usually, schematics have no errors. Constraint files and other documentation frequently have errors.

If, you intend to do software debugging of your CPU cores, then you probably want a different circuit than the board level JTAG chain that the board's FPGA and FLASH devices are connected to. Sometimes ZYNQ boards have a separate header for ARM core debugging that's separate from the hardware JTAG chain.

Edited July 5, 2023 by zygot

[cmenende]

 

3 hours ago, zygot said:

think that you have that backwards; you don't need pin locations unless you intend to use the configuration specific pins as general purpose IO post configuration. For a general purpose board like Digilent sells I don't know of any application that needs to do this. The constraint files are for assigning IO to your FPGA HW application. You don't need this information ( usually ) for configuration. Usually, schematics have no errors. Constraint files and other documentation frequently have errors

I don't really agree. In order to porgram the device, VIVADO has to know where it has to generate an output signal or where to get one. 

 

3 hours ago, zygot said:

If, you intend to do software debugging of your CPU cores, then you probably want a different circuit than the board level JTAG chain that the board's FPGA and FLASH devices are connected to. Sometimes ZYNQ boards have a separate header for ARM core debugging that's separate from the hardware JTAG chain.

I know that it is possible to do it in this board. I was just searching answers for the J10 port configuration.

 

Finally I manage to connect my HS2 and to establish communication via a PMOD. 

 

Nevertheless, I still think that if Diligent offers a J10 port,  the user should be able to use it.  And for that the information required with it.

And thank you very much for your time and patience 🙂

[cmenende]

 

3 hours ago, zygot said:

All of the Series 7 FPGA boards from Digilent use an FTDI USB bridge device for configuration and as a UART. I figure that you would just configure your FPGA and use GDB using J6. As I mentioned, you can connect 2 JTAG devices to your board.

Since I have been able to connect the HS2, I am going to try this way too! Thank you again!

[zygot]

Oops, my fingers quit before finishing the text. I've corrected the original post above.

You can not use J6 and J10 at the same time. I suggest picking either the HS2 or the J6 PROG USB connector. Either way, you will be able to use Vivado to configure the FPGA or debug the HDL. For GDB I believe that you will need to make additional provisions for doing software debugging; that is additional FPGA design and resources. These may well be in your cores, if they are designed explicitly for a Series 7 FPGA device.