enable FMC pins through constraints.xdc

[Ismail]

Dear Team,

We are in process to interface our application over the FMC connector (160-pin FMC LPC connector) in Nexys video artix-7 200T board. We are looking forward to enabling the FMC  pins using the constraints.xdc,  and are stuck up   to fetch signals from onboard FMC pins. We would like to clarify the following commands with you  for enabling the signals over the onboard FMC pins.

 

As per the Nexys video manual, the voltage is adjustable and instructed us to set in the constraints.xdc as vadj   for a default value of 1.2V(please refer to the below scripts). Unable to get the same Voltage or power from the fmc. Please find our program scripts for the VADJ and the FMC in the constraints.xdc. We need your cordial support to review the constraints file for Nexys Video Artix-7 board, and guide us to execute our application. We would appreciate you sharing the demo / example files to enable the vadj, fmc and set the values for set_vadj[1:0] pins for 3.3V in nexys video board.

 

## Voltage Adjust

set_property -dict { PACKAGE_PIN AA13 IOSTANDARD LVCMOS25 PULLUP true } [get_ports { set_vadj[0] }]; #IO_L3P_T0_DQS_13 Sch=set_vadj[0]

set_property -dict { PACKAGE_PIN AB17 IOSTANDARD LVCMOS25 PULLUP true } [get_ports { set_vadj[1] }]; #IO_L2N_T0_13 Sch=set_vadj[1]

set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS25 PULLUP true } [get_ports { vadj_en }]; #IO_L13N_T2_MRCC_13 Sch=vadj_en

## FMC

set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS12 } [get_ports { gpio0 }];

set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS12 } [get_ports { gpio1 }];

[zygot]

To my knowledge Digilent has never published a design that changes the Nexys Video Vadj voltage.

According to the boards' reference manual, if VADJ_EN is low, then the regulator providing Vadj is disabled, so 0V. The reference manual is in error about any "default" value for Vadj. Once VADJ_EN is asserted to a logic high state, the regulator drives Vadj to be 1.2V, 1.8V. 2.5V or 3.3V according to the state of the 2 SET_VADJ output pins. There will be a delay before Vadj becomes stable. If you use the high impedance PULL_UP constraint on all of the output pins that control that regulator you will get Vadj = 3.3V, maybe.

According to the reference manual you should not change the state of the SET_VADJ outputs while VADJ_EN is asserted.

It's possible to assert pin outputs to  default value that isn't 0. If you don't want to do that then your design has to bring up the Vadj power supply explicitly.

One way to do this is to have an up counter control these pins after configuration.
  -- a counter to set the Vadj voltage
  -- Need to use a clock that is always available and isn't from the FMC connector !!!
  vadj_count_proc : process(clk100,areset)
  begin
    if areset = '1' then
      vcnt <= (others => '0');
    elsif (rising_edge(clk100)) then
      if vcnt < X"FFFFFFFF" then -- important to stop counting before overflow...
        vcnt <= vcnt + 1;
      end if;  
    end if;                                                                       
  end process vadj_count_proc;     

  -- To change Vadj we need to do this:
  --  VADJ_EN   <= '0'  disable the regulator
  --  SET_VADJ  <= sets the Vadj voltage: {0,1,2,3} --> {1.2V, 1.8V, 2.5V, 3.3V}
  --  VADJ_EN   <= '1'  enable the regulator
  --  VADJ_EN = '1' and SET_VADJ = "00" when the FPGA is not driving these signals
  -- We need Vadj to be 2.5V so                    
  set_vadj        <= "10" when vcnt > X"00FFFFFF" else (others => 'Z'); -- set to 2.5V 167 ms after configuration
  vadj_en         <= '1'  when vcnt > X"01FFFFFF" else '0';             -- enable the Vadj control 336 ms after configuration

Some designs using an FMC mezznine card may bot want to reset vcnt after configuration as shown above.T

This user selectable Vadj arrangement was poorly thought out. I can't think of case where one would want to change Vadj after configuration. The Genesys2 that followed the Nexys Video has a more practical and safer power supply design.

As for "enabling FMC pins", I assume that this is a translate into English artifact. The FPGA IO connected to the FMC connector are always enabled if your design provides proper location constraints and the toplevel entity of your design includes them on the IO port. The problem is making sure that the voltage powering the Vadj banks have compatible IOSTANDARD assignments as the logic on the FMC carrier board. That's the potential problem with how the Nexys Video board sets Vadj.                                              

Edited June 28, 2023 by zygot

[Ismail]

Thanks for your information I have been requested to share my queries,

My first request to share a  document or manual for mapping/enabling the FMC pins in the constraints file. we refered https://github.com/Digilent/digilent-xdc/blob/master/Nexys-Video-Master.xdc for writing the constraints for enabling fmc pins.

Please find my Constraints script for enabling the FMC pin of G21 (GPIO0) & G22 (GPIO1) 

## FMC _ Constraint file

set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS12 } [get_ports { gpio0 }];

set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS12 } [get_ports { gpio1 }];

 

 

[JColvin]

Hi @ISP,

As zygot mentioned, uncommenting a line in an xdc file does not "enable" a pin.

A different way of phrasing of what the .xdc file does is tell the Xilinx software what a particular "pin name"/entity in your design, such as 'gpio0' in your example, where you want it connected in the hardware and what attributes or characteristics the software should expect that pin to have while the software is synthesizing, implementing, and generating a bitstream for your design.

So for example on your line here:

Quote

set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS12 } [get_ports { gpio0 }];

You are telling the Xilinx software that the 'gpio0' that you are using in your design is assigned to pin F19 on the FPGA and that it will have a IO voltage standard of 1.2 LVCMOS. The pin itself is already "active"; you are now just telling the software that pin F19 will be the one that does everything that 'gpio0' uses in your design.

To be clear, as is, what the quoted line does not do is make the pin F19 an input or an output, or set it to a logic high or a logic low state; that will all be defined and done in your design.

The catch with all of this is that this will only work if you want the signals to be operating at 1.2 V as that is what you told the software that you expect the voltage to be (and what the power supplies on the Nexys Video will power that particular that FPGA bank at by default).

If you want or need a different FMC voltage you will need to adjust it as zygot (and the reference manual) described by setting the VADJ_EN pin to a logic low value, then adjusting the SET_VADJ(1:0) pins to your desired voltage level output, then setting the VADJ_EN pin to a logic high value; I would do this in an approach much like zygot suggested, as zygot is also correct that Digilent does not have (at least as far as I am aware) a published design that demonstrates this change in action. Additionally, if you adjust this supplied VADJ voltage and happen to use other pins in the same Bank 15 or Bank 16, you'll need to tell the software via the .xdc file what voltage those pins are operating at.

Let me know if you have any questions.

Thanks,
JColvin

[zygot]

@ISP, Is your other name Chat GPT-4 by any chance? If it is, then this conversation makes a whole lot more sense...

Edited June 30, 2023 by zygot