dvi2rgb Error [DRC PDRC-34] when using 1080p dvi2rgb IP on Vivado 2022.1

[Savotage]

Hello I am using the HDMI Demo for the Nexys Video board in VIvado 2022.1 using the project linked in this forum post. In short I am trying to pass a 1080p video signal through the FPGA and when I try to raise the dvi2rgb (V2.0) IP's TMDS clock range to support 1080p input (the output already works at 1080p in the project as provided) I get the following error:

[DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 400.000 MHz (CLKIN1_PERIOD, net CLK_IN_hdmi_clk) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X1Y2 (cell hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator) falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1200.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please run update_timing to update the MMCM settings. If that does not work, adjust either the input period CLKINx_PERIOD (12.500000), multiplication factor CLKFBOUT_MULT_F (5.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

If I switch back to <120 MHz as shown below, the project can be implemented without issue and works on the FPGA as outlined in the demo, the only hitch being that it can't record input videos at 1080p, but lower resolutions are passed through just fine as long as the output resolution matches or exceeds the input resolution. (This might be worth mentioning on the HDMI demo page instead of the absolute of 'no' video recording working).

How can I address this issue? I feel there may be an issue in the IP with how the timers are set up but I am not confident enough with my understanding of primitives to go digging about in there myself.

The only other mention of such an issue I can find is in this thread but they had issues with the VCO frequency being too high and were using VIvado 2017.4, with the fixes incorporated into V2.0 of the dvi2rgb IP which is used in this project.

[Savotage]

I have made some progress on this, where I can now make a bitstream without a failure.

The fix that brought me here was back tracking that "CLKINx" signal mentioned in the error message and seeing if I could adjust the period, this signal is derived from the "TMDS_IN_clk_p" signal which has a period defined in the master constraints file ("NexysVideo_Master.xdc") on line 54 to be 80 MHz, but I brought it to a bit above 120 MHz by changing it to the following:

create_clock -period 8.000 -name tmds_clk_pin -waveform {0.000 4.000} -add [get_ports TMDS_IN_clk_p];

Hopefully this helps someone else. However, 1080p doesn't seem to be read/passed through anyways, the screen just goes black. Lower resolutions around 720p work though. I'll be sure to put any other fixes that help me along.