waveformssdk DigitalIn Acquisition with external clock source (ADP3450)

[yusuke_Adv]

I am using the logic analyzer function of the ADP3450 to make measurements.

DIO0 pin = clock signal (5MHz)

DIO1 pin = 1 bit stream (5Mbps)

In this case, sampling clock source is not internal clock, but DIO0 pin as external clock signal.

I managed to capture data by using the Waveform GUI. Now I am trying to figure out how to do this with Waveform SDK.
The preferred programming language is python. But any other language is also acceptable.

I have checked the python script example bundled with the Waveform SDK.(example/py/DigitalIn_Acquisition.py)

 

I have two main questions.
Question1: How do I set the DIO0 pin as Sampling Clock in Waveform SDK?
I assume it is possible to assign DIO0 to Clock Source using FDwfDigitalInSampleFormatSet(), but I don't know how to do that.

Question2: Can you give me any comments on the read data structure of FDwfDigitalInStatusData()?
What values can I see for the DIO1 pin data?

[DigitalIn_Acquisition.py]

Quote

 

# 16bit per sample format
dwf.FDwfDigitalInSampleFormatSet(hdwf, c_int(16))
...
...

# get samples, byte size
dwf.FDwfDigitalInStatusData(hdwf, rgwSamples, 2*cSamples)

Edited June 20, 2023 by yusuke_Adv
typo

[attila]

Hi @yusuke_Adv

If you are referring to the Sync mode in Logic Analyzer see the WF SDK/ samples/ py/ DigitalIn_Sync.py

Another option would be using the external clocking mode which is available in mixed mode. 
For this configure the configure the analog-in to use trigger line as clock and for digital-in use FDwfDigitalInClockSourceSet(, DwfDigitalInClockSourceExternal2) so digital-in to use analog-in sampling.

[attila]

Hi @yusuke_Adv

Yes, dwf.FDwfAnalogIOChannelNodeSet(hdwf, 0, 0, c_double(1.2))

[yusuke_Adv]

Yes. I am using the Sync mode in Logic Analyzer. Your advice is very helpful.
After reading the sample scripts you mentioned(DigitalIn_Sync.py), most of my questions have been answered.
I will give it a try.

[yusuke_Adv]

The input signal amplitude to DIO0, DIO1 is 1.2V (0~1.2V)
Sorry to keep asking this question, but, could you comment on how to set the Digital In threshold level (e.g. 750mV)?
Or could you let me know which sample script is helpful?

Edited June 20, 2023 by yusuke_Adv

[attila]

Hi @yusuke_Adv

See the WF app Help and SDK manual pdf

[yusuke_Adv]

@attila
Thank you for taking the time to help me out.
Sorry for the confusing question, but I understand how to set DigitalIn threshold by Waveform's GUI, as you attached the screenshot. What kind of Waveform SDK API (function) should I use to achieve the same operation? 
Are you saying I should use FDwfAnalogIOChannelNodeSet() function with follwing arguments?
idxChanel=0
idxNode=0
value=1.2

According to the reference manual, the arguments of the FDwfAnalogIOChannelNodeSet function are defined as follows

Quote

FDwfAnalogIOChannelNodeSet(
HDWF hdwf, int idxChannel, int idxNode, double value)
Description: Sets the node value for the specified node on the specified channel.
Parameters:
- hdwf – Open interface handle on a device.
- idxNode – Node index.
- idxChannel – Analog I/O channel index of the device.
- value – Value to set.

I would appreciate your help.

[yusuke_Adv]

@attila
Thanks a lot. I appreciate it.
I'll try it.

[yusuke_Adv]

Hi, @attila

I have successfully captured logic analyzer data in Sync mode by WaveformSDK using the method you described.

This is a little different from the last case, but I would be happy to receive your comments.

In this case, we want to capture Clock connected to Triger1 in Mixed Mode with 16bit width (DIO15-0).

DATA : DIO15-0, 3.3Vpp, 78.5Kbps x 16pin
Clock : Triger1, 3.3Vpp, 78.5KHz

We are thinking that with mixed-mode, we can sample to 78.5KHz clock edge. Is there any restriction on the frequency that can be used as the Sampling Clock for Triger1?
According to the Help page, 10MHz~50MHz when using Triger1 as an External reference clock, is it OK to use a slower sampling clock frequency like 78.5KHz in Mixed-mode?

From what I have actually tried, there seems to be no problem. This is the actual logic waveform captured in Osciloscop's mixed-mode.


 

[attila]

Hi @yusuke_Adv

No, the reference clock is the input of a PLL that requires at least 10 MHz.

[yusuke_Adv]

Hi, @attila

Sorry for the repeated confirmation,but when using the Trigger 1 port as a sampling clock in mixed-mode, it needs to be set to 10MHz or higher, am I right?

Trigger1 port is selected as a external sampling clock in mixed-mode.(As shown in the figure below)
 
In addition to the above, I am not sure about the following point.
Does the Trigger1 port as a external reference clock mean the same thing as using it as an external sampling clock in mixed-mode? 

Edited June 26, 2023 by yusuke_Adv

[attila]

Hi @yusuke_Adv

The Reference Clock (10-50MHz) configured under Device Options will make the device use this (multiplied to be 50-125MHz), instead of the internal oscillator for the entire device, driving ADC,DAC,DIOs.. This ensures no jitter or drift over time between such synchronized devices.
With Sampling Clock (<50MHz) the device runs at the specified frequency (50-125MHz), the device logic looks for edge on the trigger line and stores the last samples (or delayed). This can be used at arbitrary frequencies but the jitter will be about 10ns, the period of the specified system frequency.

[yusuke_Adv]

Hi @attila

I was able to figure things out because you helped me.
I appreciate your support.

Edited June 27, 2023 by yusuke_Adv