SREC SPI Bootloader not working

[Mario875]

Hi all, I am trying to get my project to boot directly from flash memory, but as requires a lot of BRAM, I am trying to use a bootloader to load up the application and run directly from the DDR memory I have.

 

If I dont use a bootloader and run my application directly from MicroSD it works fine, but then needs a lot of BRAM and as I want to move this to a smaller FPGA later on a custom board I need to reduce the BRAM utulisation and to do that I need to run from DDR and use a bootloader.

 

So far I have done the following...

 

1. Created HW design in vivado with QSPI IP on a 50MHz clock at ext_spi_clk and generated bitstream
2. Created my SW application in vitis and assigned all to DDR
3. Created a new application in vitis for the bootloader and assigned all to BRAM
4. Configured the blconfig.h to look for my application at 0xA00000 (10MB into the 32MB of QSPI)
5. Built all and generated a bootloader.elf as well as my application.elf
6. Generated a download.bit file using my project.bit, project.mmi and bootloader.elf (download.bit size is 9.5MB)
7. Programmed the download.bit file to QSPI via "Xilinx -> Program Flash" at offset 0x0 (no offset)
8. Programmed the application.elf at 0xA00000 as per the definition in step 4

When I do the above I get the info below in the Vitis Serial Terminal:

[quote]SREC SPI Bootloader
FlashID=0x1 0x2 0x19

Loading SREC image from flash @ address: 00A00000[/quote]

Then nothing happens! I assume the bootloader is seeing the flash as it shows a flashID not equal to 0!

I have read back the .bin file from the QSPI device and can see there is data that begins at 0x00A00000 (see image attached), so not sure what is going on, any ideas? Also attached a snippet of how I have the QSPI IP configured.

 

This is on a Digilent Nexys Video dev board with Artix-7 XC7A200T FPGA.

 

[Mario875]

Right, so interestingly enough just after posting I found this thread... 

It points to an ELF bootloader on Github (https://github.com/henrikbrixandersen/elf-bootloader), I downloaded that and added it to my project (removing the SREC SPI loader) and it just works!!

 

I had a slight issue with Vitis where it simply would not let me flash a raw .elf file, it says its a valid file to use when flashing, but then it kept complaining about a missing .bin file, so as the ELF bootloader wants a raw elf file with the '.ELF' header in the hex code I simply took the application.elf file and renamed it to application.bin, then Vitis programmed the SPI flash with that file in the location requested and now it works!

 

It is also a bit smaller than the SREC loader (10kB with heap & stack vs 17-18kB with heap & stack). If I can get rid of the heapt & stack and have it still work I may even be able to reduce the BRAM on my MicroBlaze down to 8kB.

 

Something isnt right with either the SREC SPI Bootloader or in the way Vitis is converting the .elf into SREC it seems. I have noticed the SREC file is only ~634kB where as my ELF file is 1,134kB! Could it be something to do with that??

 

HOWEVER...it does still take 25-30 seconds from power on to configuration completing (config itself is very quick, its about 23-24 seconds before the bootloader even starts doing its job), is there any way to speed that up?

 

Also, when I reset the MicroBlaze using a push button the bootloader does not re-start and re-program the DDR memory with my application, so I need to reprogram the entire FPGA using the 'PROG' button the the Nexys Video. Any ideas on why the bootloader doesn't reset when I reset the MicroBlaze? I have noticed the reset works fine with my application on its own or with the SREC SPI Bootloader, just not with this ELF Bootloader I found??

Edited June 11, 2023 by Mario875

[JColvin]

Hi @Mario875,

I've always had a terrible time getting the SREC bootloader to work successfully, so I've usually resorted to associating the .elf with MicroBlaze in the Block design (https://forum.digilent.com/topic/23536-storing-program-in-flash-on-cmod-a7-in-2022/, https://forum.digilent.com/topic/21966-flash-programming-cmod-s7-with-microblaze/, and what I believe this user ultimately ends up doing on this post: https://forum.digilent.com/topic/19801-issues-with-microblaze-in-arty-a7-and-using-spi-flash/) but that of course eats up BRAM which you stated you were limited on.

I did find a different thread where a user may have gotten the SREC working in Vitis, but I haven't stepped through all of their posts to confirm this: https://forum.digilent.com/topic/22582-cmoda7-35t-vitis20212-microblaze-and-srec-bootloader/.

On 6/11/2023 at 4:31 AM, Mario875 said:

HOWEVER...it does still take 25-30 seconds from power on to configuration completing (config itself is very quick, its about 23-24 seconds before the bootloader even starts doing its job), is there any way to speed that up?

I don't have much insight on making the application load faster though; you seemingly already have the block design set to use Quad SPI, so unless the Elf Bootloader you found is not properly taking advantage of that, there won't be much to do to speed up the flash memory outside of making sure it is being clocked at the highest supported rate (the IP looks like it is using a fixed frequency ratio of 2, which divides down the incoming clock by 2 to generate the SPI clock, though of course you'll need to make sure that the highest rate for the flash isn't only for reads / only for writes, see Xilinx's Product Guide for more details: https://docs.xilinx.com/r/en-US/pg153-axi-quad-spi/AXI-Quad-SPI-v3.2-LogiCORE-IP-Product-Guide) or increasing the FIFO depth from the minimum of 16 to a higher value.

On 6/11/2023 at 4:31 AM, Mario875 said:

Also, when I reset the MicroBlaze using a push button the bootloader does not re-start and re-program the DDR memory with my application, so I need to reprogram the entire FPGA using the 'PROG' button the the Nexys Video. Any ideas on why the bootloader doesn't reset when I reset the MicroBlaze? I have noticed the reset works fine with my application on its own or with the SREC SPI Bootloader, just not with this ELF Bootloader I found??

This might be able to be resolved by changing the build configuration in your Vitis application from Debug to Release (I feel like I've heard mixed results on this though). I would have to go digging more into how the reset flow works with bootloaders on Xilinx devices to be able to give a more confident answer.

I don't have any immediate insight into your other questions or comments at the moment unfortunately, but I'll let you know if I happen to come up with something later.

Thanks,
JColvin