ZMOD ADC 1410 questions

[Paul Chang]

Dear Sir,

I have two questions below:

1. Eclypse z7 and ZMOD ADC 1410 

When I use TCP_perf tcp_write library in Vitis,the error message 'xps_ethernetlite drivers not present' will occur.

Could you tell me how to solve it? 

Plain text test data (ex:0123456789...) is no problem.

 

2. I would like to implement ZMOD ADC 1410 with Genesys ZU 5EV.

In Vivado, the ZMOD library seems can not update IP well. Any suggestion? Please see picture below:

 

Best Regards,

Paul

Edited June 6, 2023 by Paul Chang

[artvvb]

Hi @Paul Chang

Some images didn't come through for the TCP issue. It sounds like the library is trying to use an EthernetLite IP in PL, rather than the PS ethernet controller. The PS controller should be enabled by default. I assume you are trying to use the PS controller connected to the onboard ethernet jack, and that there is no ethernet IP instantiated in PL?

For The locked design errors, the way to clear those particular errors is to use the Tools -> Report IP Status menu option, then Upgrade All. That said, unfortunately, the Zmod ADC/Scope and Zmod DAC/AWG controllers do not support the Genesys ZU at this time. As I understand it, the controllers rely on some 7-series specific primitives.

Thanks,

Arthur

[zygot]

On 6/28/2023 at 8:37 PM, artvvb said:

unfortunately, the Zmod ADC/Scope and Zmod DAC/AWG controllers do not support the Genesys ZU at this time. As I understand it, the controllers rely on some 7-series specific primitives.

I don't know for sure why this is true. I've used the low-level ZMOD controller sources and I've done some designs with UltraScale+ ZYNQ devices.

I suspect that the problem is that, in UltraScale, the IO is completely different for advanced IO features like DDR. The general purpose IO that was on the Series 7 devices isn't so general purpose on UltraScale devices as they are designed to implement Gbsp+ LVDS in quad groupings. What was fairly straightforward as Series 7 DDR can get really complicated in UltraScale, even if you carefully selected your IO assignments.

I believe that someone at Digilent should present a more informative answer to their Genesys ZU customers. If the problem is finding someone to write HDL code that's one thing. If the problem is that the SYZYGY FPGA pins were assigned as if it were a Series 7 device, then that may well be a much bigger problem to solve, if it's even solvable. 

Edited July 3, 2023 by zygot

[artvvb]

This article talks through changes required to get the Scope 1410 working with a Genesys ZU: https://www.hackster.io/pablotrujillojuan/single-tone-detector-with-genesys-zu-and-rtu-728c3f#toc-developing-zmod-adc-driver-for-genesys-zu-6. Primarily switching out IDDR primitives, and some differences in how to generate the clocks for it as opposed to what can be seen in Eclypse examples. Timing constraints may also be affected, there are some comments and Eclypse-specific timing parameters in the generated constraints.

There's more information on the ZU's SYZYGY port and how its pins are mapped to I/O pins in the manual: https://digilent.com/reference/programmable-logic/genesys-zu/reference-manual#zmod

Thanks,

Arthur

[zygot]

@artvvb,

Well, the two links above provides some more information, as far as it goes.

I tracked down the references for the ZMOD 1410 ADC pod on a Gensys ZU board that you provided, as well as the pertinent reference manuals.

Looking at the zmod_adc_driver_v1_1.v source, DDR is implemented with the UltraScale IDDRE1 primitive. For what it's worth, according to ug571 UltraScale Select IO Users Manual, IDDRE1 when instantiated in a design is 'translated and implemented by Vivado as ISERDESE3'. HP IO Banks do not support 3.3V or 2.5V signalling.

According to the Genesys ZU Reference Manual: The (SZGYGY) differential pairs were prioritized and wired to HP banks, allowing the maximum data rates supported by the SelectI/O architecture. However, the single-ended pins are wired to an HD bank.

According to the ZMOD_1410 schematic, all of the ADC DDR data outputs are assigned to single-ended SYZYGY pins except for DOUT_ADC_2, DOUT_ADC_3, DOUT_ADC_4,  AND DOUT_ADC_9 all of which share a differential pair with another single-ended signal.  The CLKIN_ADC input to the pod is differential and assigned to differential pins while the CLKOUT_ADC signal is single-ended and assigned to a differential pin.

From what I gather, the Genesys ZU SYZYGY port is lucky that the data rates for the current batch of ZMOD converters is in the 'low performance' range. I can't assert that the third party demo projects that Digilent uses to promote these boards can't work properly, but I'm not too thrilled at the execution either. It would certainly be better, for everyone,  if Digilent engineers bothered to do demo designs for their own boards.

 

Edited July 5, 2023 by zygot