Dear Sir,
I have implement my design in CMODA7. (Also mount a 100Mhz oscillator with CMODA7)
My three idelay2 modules are FIXED mode. Taps are 0 ,0 ,0
50Mhz is my input signal.
simulation: DATAout1:3.915ns , DATAout2: 4.736(3.915+0.821)ns , DATAout3: 5.762(4.736+1.026)ns
measurement: DATAout1:4.044ns ,DATAout2:5.088(4.044+1.044)ns ,DATAout3: 6.445(4.044+1.044+1.357)ns
I would like to know why three Taps of idelay2 are all zero but their delay are different.
Best Regards,
Paull