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Arty A100, weird clock speed on xdc file



Hi all, first lets check the oficial time of the Arty A100.


From the page we know the A100 have 450Mhz.

While in the oficial xdc file from github we have:

create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];

1/10ns is 0.1Ghz, which is the 100MHZ....

So, what is the right clock speed for the FPGA?


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The input clock from the external oscillator is 100 MHz. The "450+ MHz" internal clock speed listed is based on maximum switching speeds within the FPGA fabric. The 100 MHz input clock can be used with clocking resources, MMCMs and PLLs, to generate various other frequencies of clocks including ones faster than the input.

More info can be found in this Xilinx thread and in the Artix 7 datasheet.



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With something like that... how should be the best way to do an UART? with an external clock? it has a rang too wide to set a constant baud rate..... maybe with the use of $time?

Tthe frecuency goes from 100Mhz to 1Ghz!, UART is too sensible, now I don't have idea how UART works while the clock can changes so much.

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