latot

Hi all, the Impedance Analyzer is great, but I'm not able to found something, rn it get samples from different frecuencies, for each frecuency it must sample a min time, so a lower frecuency need more time. There is a exception to this rule, is for frecuency 0, which means a constant voltage, this could be the same to ask the resistance in the simplest ohm law, but I'm not able to found how to do this from the analyzer. Thx!

With something like that... how should be the best way to do an UART? with an external clock? it has a rang too wide to set a constant baud rate..... maybe with the use of $time? Tthe frecuency goes from 100Mhz to 1Ghz!, UART is too sensible, now I don't have idea how UART works while the clock can changes so much.

Hi all, first lets check the oficial time of the Arty A100. https://digilent.com/shop/arty-a7-100t-artix-7-fpga-development-board/ From the page we know the A100 have 450Mhz. While in the oficial xdc file from github we have: create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }]; 1/10ns is 0.1Ghz, which is the 100MHZ.... So, what is the right clock speed for the FPGA? Thx!

mm, I think I just get confused, I use to do all tests over the FPGA then I thought... I need to learn to use the simulator, but I didn't expected the clock is not initialized by vivado. Thx telling me :) I'm looking on guides and similar to continue learning. thx!

Mmmm, I try the testbench, well is tricky and is able to simulate the clock, but why the clock does not works now with the blinky example?

Hi all!!, I has been able to use Vivado simulation in the past, but now..., I don't have idea why, the clock is always Z in the simulation... I tried to create a new project, selected: Board: Arty A100 XDC: https://github.com/Digilent/digilent-xdc/blob/master/Arty-A7-100-Master.xdc Then in the xdc uncomment: set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }]; set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L24N_T3_35 Sch=led[4] In a file where I had the blink led example: `timescale 10ns / 1ns module blinky( input CLK100MHZ, output led ); reg[30:0] count = 0; assign led = count[10]; always @ (posedge CLK100MHZ) begin count <= count + 1; $display("%d", count); end endmodule Then I go to Simulation > Run Simulation, but... the clock will be always on Z, this does not happens before, and I don't get why does not works now.. Thx!

Hi!, I was just checking, now in vivado, the constrains are empty by default, that means now selecting the board does not add the xdc .... we need to add it manually, but how the repo does not have it... now vivado says the boards does not have any connectors on the project.

Hi all!, Here again with more weird questions :) From the start, FPGA is presented to be able to create "circuits" in a dynamic way (verilog, vhdl, any language we wants), it is great, is just that when I was testing I realizes in the guides, I wasn't able to find a good description of how the timing works. In my basic and maybe inaccurate explanation, there is some things the I would to know better. Clock: All the FPGA have a clock, and the clock have two stages, posedge and negedge. Circuits: Th circuits that are used by the FPGA. Is difficult to me talks about this, because if I talk about one thing that confuses me, it will open a new one too so... The clock, the we know i has a frequency, but... when it will apply the circuits? because for example, the FPGA will mode from posedge to negedge, to do this, all the new circuits must run on the actual values of the memory/wires, but if one value changes, that would cause some values to be updated with wrong values (the new ones). Obvs, the actual FPGA probably already have a way to solve this, so what is the question? well when we simulate a circuit in vivado, the change from posedge and nedgedge is... instantaneous.... that is what I don't get, in the middle of it there should be this system that handle part of the FPGA integrity. Maybe the simulations does not show it, and there it is... I feel like someone will tell me, check this link about how FPGA works.. xD Oks now... circuits!... how to handle circuits, we build circuits, they must be reminded, the question would be how the circuits are handled. Lets pick as example, "wire" signal, a wire must be connected all the time!, yes or yes, some circuits are sensitive, but how is handled in a consistent way? how are the circuits keep consistent in all the work? I read some of this is not perfect, we can check that in: https://verilogguide.readthedocs.io/en/latest/verilog/procedure.html#guidelines-for-using-always-block There is some cases where we get weird things working with the clock, and assignments... Even after all this, is possible that there is no a general answer to this, because every problem maybe would be fixed in differents FPGA... If everything works like the theory says, probs the second part of this questions would not exists :) Thx!

Hi, The Scope is still capturing the same waveform that was being generated by the Wavegen. Mmmm, is not the same, stop the WG to uncheck "Enable"? If I close the tab, it stop in the moment, well If I put more zoom and samples probably I'll be able too see some time for it to stop. Is a little weird if it need so much time to stop the signal.

Hi all, I found a problem with WaveForms, actually I have connected WG and the Scope with a resistor in the middle, 1V DC, I start the WG and the Scope, all seems right in the Scope, but...., when I stop the WG, I notices the Scope still shows corrent, it didn't stop!, but..., it stop if I close the tab of the WG in WaveForms.... Thx!

Yay!, things is getting form, due to some explanations before, I wasn't able to get a very basic thing, UART sends bit a bit, one every baud. All the start bits must be 0. All the end bits must be 1. 'U' has the next bin code '01010101', so, send a lot of 0 and 1 interspersed will show us the 'U'! :O that is a nice way! That also means, the UART keeps the signal in the baud time, independent from the CPU/FPGA clock, in that case.., would be good check this behavior is keep from the FPGA to the FTDI. The actual CPUs does not has a stable clock time, they vary, but I don't know if the FPGA has a stable frequency or not. At least from the CPU perspective, the only way I'm thinking it can works with UART is having an extra/independent clock to sync the port in the pc. If the FPGA does not has a stable block..., that could cause several issues, thinking in the future to put it to work very hard :) (cooling it would be a point too) Maybe I would need an external clock too? maybe due to variations of the clocks (FPGA/PC) we need a +-5%? I think I don't get very well how the UART keeps the sync in longer times, maybe with time is easier to loss one bit and delay all the data we are reading breaking the start/stop bit for example. I don't know if UART has a way to tell use, "hey! this packet is broken send this again!". Thx!

Hi!, I'm really emotional of the great help and answers here :) I already read all of them, but I think I'll need to read again some parts. Great explanations @reddish and @zygot! Now I feel I know better with what I'm treating :D Due to the story of Serial and UART is needed to know the history to know how to implement it. I first started with blinking a led, then playing with the frequency and buttons, very basic, I want move to more complex projects, that is why I want to lean UART, well the true is I search in google how to connect FPGA with the PC and the answer was UART, maybe there is a easier or better way, but I think get the experience can be great. I think have a way to connect FPGA with PC is the minimum to test more complex projects. There is Ethernet too, probably I'll check it, but later. I'm still not used to use the simulation of Vivado, I'll work on it, thx for the advice. I'll be checking later the project Zygot, thx for the reference!, I want first understand the basics of UART. I think Verilog is not hard, let me explain it, we can know play chess, or at least learn the rules, but know the rules does not do us good in chess, here is similar, verilog is the pieces, rules and board, while our opponent, would be the... our goal and the nature of the hardware (different to software). While we learn to play better with the FPGA we learn to use better the pieces, use the board, take advantage of them with the rules. So as a first part learn Verilog is not that hard, while we can do the mental switch of "you are working with hardware, connections not software" and have a place that explain use how it works clearly. To understand well verilog the tutorial I put above helps a lot :) In my case, probably can't call my self newbie in programming, designing, modeling and that type of things, that would be an advantage I have. From there, if anyone would like to enter to learn FPGA with verilog without know algorithms, I think there will even more hard parts than the ones I wrote. Maybe, would be easier to learn the basic in python to know algorithms and how to think/design them than start directly to FPGA/Verilog, is a lot more flexible and less technical, and easy even if you learn a lot of libs. I didn't put here, I'm using an Arty A7-100T. Thx for the help!

Hi all, I'm trying to learn verilog, I'm new in the FPGA world, I got the very basics of verilog, and one very important thing is how to communicate the FPGA with a computer. To who is written this.., well anyone interested in newbies difficulties, who want to write guides, and for Digilent too. I want to ppl understand here, why is hard for a newbie learn UART, even before the implementation. I want you to understand why I can't understand. And later, in case I succeed to show you that, help me and others, to learn UART in a better experience and with that, open more the FPGA world, I still can't understand very well UART. Sorry if this text is too long, or even sounds too pretentious. Personally, has been too hard to get how works verilog, verilog is not difficult, but is hard to find documentation that understand its own common sense, ppl a lot of times tries to explain (with good will) but didn't notice that a lot of words, concepts, logic states of the guide/project are still not explained, so ppl will not be able to understand what they just don't know, well I found a doc about verilog very good about it. I think is the most complete I have found, read from the start to get it, special for newbies like me: https://verilogguide.readthedocs.io/en/latest/ Oks, go to the topic, I have checked a lot of videos, longs and short ones, codes of github, guides, and there is always a point where something is not explained and I ends in confusion. I would appreciate don't says, "read this one", one reason why I can't understand very well this is due the same as above in verilog, there is common sense and experiences that a newbie does not have way to know. You will understand this better later, I wrote that down :) I want to understand UART, I think is great to then can construct more robust projects, so the point is not just test and found "it works". I like Digilent due to the opportunity to learn FPGA, I think would be great have projects in different languages, the repertory of type of projects is big, but usually every project is in one or other language, the blink led is in verilog, the GPIO (and UART) in VHDL, does not help to learn D: A hardest part of the UART protocol, is not the protocol it self, FPGA controls bit a bit. Well, an FPGA does not need to come with UART, but we can buy a PMOD and connect it (or come with one integrated how the one I have), and we can know UART also has a protocol, now some questions, who follow the protocol?, how much of the protocol the PMOD handle, and how much we need to implement in the FPGA? Maybe even, the PMOD uses the UART protocol for the PC but uses other protocol in the FPGA connection! but why? maybe who design it found a easier way to send the data from the FPGA to the PC using the UART protocol. Then there is the same questions for the UART from the PC... Maybe this is silly for you, but for a newbie like me this is just a mist of confusion. To can understand UART is not enough know Verilog and UART protocol, there is a mix of experience, and common sense, things that are usually not written. I though, well, what would be a newbie explanation that anyone can understand about the UART data flow? I want to take advantage of my current newbie status to get a clear way of it. My answer now was, examples!, what? there is a lot of examples out there!, yea, they explain a lot of things, but did you remember? usually every example has a sections that are not explained, add what I wrote above, is not like a newbie can fully understand any example. I think before the example, explain the steps is good, but probably we will not be able to understand the big picture. Imagine an example like this, and we want from the FPGA send '11101010101', what would be flow of information? what would be the step 1?, step 2?, step 3?, how is used and splited the data? you maybe will says, there is a lot of guides that does that exercise, but..., not completely, when you are forced to show this step by step with that data you can't skip anything, need to show what bits sends and why, justify every bit of information! FPGA ---------- PC '010010001010' -> (explain where it comes that data) '1010100111010' -> (explain where it comes) The idea would be explain how the data is send to the PC, where and how every rule is applied, a good example should be able to use all the rules of the protocol, with examples where we can see the difference between them. There is the proposal of start with the minimum applicable rules (like skip parity bit), and is good to know for example when or how it works, how a pc know there is parity or not and similar with the other rules. One advantage of something like this, is that we don't need know verilog, we only need to know the workflow of UART, this helps to understand how much of the UART protocol we need to implement in verilog, and how much its handled by the UART PMOD. Then, we can start thinking..., how can I write this workflow in Verilog?. Then, the same would be to can read data from the PC. FPGA ---------- PC <- '001010010101' (explain how we can read the data) Maybe the simplest part, is the baud rate generator, just because every FPGA has its own frequency, and UART need some specific baud rate to work and synchronize with the PC. The only weird thing about it would be that seems did not works any baud rate.., weird, but how to construct one with +-5% of error is pretty simpler, then just connect the wire, but not trivial to put for a newbie. I think I wrote everything I had in mind to explain from my newby perspective why is so hard learn UART, I decided to write like this, and give a feedback from someone who know about algorithm but not FPGA why would be so hard to understand this things, would be great if this feedback is considered in Digilent guides. I would appreciate if someone can helps to create examples to help to understand this for newbies :) The bits I choose in the transmitter are intended, a number of bits that is not 10 nor 18 (full block of data), and need at least two packets :) Thx!

Hi @attilasomeone knows how to use safe the AWG?

Mmmmm, so what would be the right values to use?, not the max/limits, the max in right to use. 10mA? The ideal power to not heat the protection. I'm thinking..., why the limit is in the current? usually the heat is proportional to the resistance, (V*I), without high voltage I should theoretically be able to get more current without more heat.

Hi hi, I'll explain everything in this topic, I want to made a fluxgate-magnetometer, to made it, I need connect a sin(w*t) wave to a selonoid (I ca get this from the AWG), then I get the output. The base concept to make one is: https://physicsopenlab.org/2019/06/06/fluxgate-magnetometer/ While the magnetic flux of a selonid is: https://en.wikipedia.org/wiki/Solenoid The magnetc flux if linearly dependant from the current, while due to the type of construction, we sould get the same voltage as the input (because we use the same numbers of turns in both places of the selonoid). For more info about the final voltage: https://en.wikipedia.org/wiki/Transformer In order to make this work, I need to maximize the current and turns, and use a voltage that the osciloscope can measure, so, too low voltage will cause a voltage the osciloscope can't measure. This requirements means, keep the wave generator working for a long time, without burn the osciloscope or the AWG, and be careful with the heat caused by the AWG. A post I make and with some info is: Thx to attila now we know the AWG can have aprox from 55mA/45mA, but as described, I don't know how much heat is generated in the osciloscope, or what are the power or current ranges that are secure for a long term usage... I would like to know recomendations about this, and how to use the AWG safely? Thx!

:O So its safe to connct directly to ground? who protect the circuit limiting the current, the wavegen or ground?

:O Thx! What is the max current the waveform can have? I don't want to burn it D: Or I can connect the waveform to a extenal ground, but in any case, I need to know the limit, or I can burn circuits inside.

Hi, I read the start, but is not like describing that, I don't want to connect the waveform generator to the scope, I want connect it to a solenoid for a fluxgate magnetometer, so, will be a connection from AWG to ground, I need to can keep the connection a long time, so heat is a good point. I need to calculate the impedance to minimize heat and maximize current, drive 10-50mA tells me there is resistance, or again, I'm confusing something, 0 impedance at output should cause high current.

Hi hi, I just want to confirm this, because if not, I can break it, when we use the waveform generator, if we connect the wave form with the ground, what would be the current? I read in the specifications that the "input impedance" is 1Mohm, so if I have a sin function of 5V, the current would be 5/1000000, 0.005mA, or I'm interpreting bad this? I know can be a silly question, but I prefer to be sure about this. Thx!

awww, there is no contact or resistance, like is not connected u.u Put a ground connector in the note and my hand helps to reduce the interference.

D: The supply have ground connection, and is working, I test it with a socket tester.

Hi, I'm having some troubles getting a good measure, particularly, touch my notebook change the reading of the Analog Discovery 2 D: Here an image, in the left the reading without touch the notebook, in the righ when touching. This was particularly weird, first, to get this type of measure, the most sensible way, is just plug a cable in the positive of the first channel and keep there, without plug to anything else (can be done connecting to negative with a little more of work). The 50Hz, seems to be the electricity in my house, just connect a AC extension closer to the measure cable, every 50Hz and proportions will raise. Now..., if I touch the usb cable, there is not much effect, just a little, but if I touch the notebook, specially the touch pad...., happens what you see up. Have my hand closer to the notebook have readings too, touch a key too D: I put the Analog Discovery 2 as far away as possible, but is the same.... My notebook is metalic. Thx!