Can't launch Vitis bare-metal application on Genesys ZU

[mossygreen]

I have a Genesys ZU board (5ev) with a Vivado 2022.2 install and am trying to follow the steps here:

https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi

After I follow the steps and get to the point of doing the "Run As" procedure, Vitis downloads the bitstream and I get an error (the full trace is attached):

Failed to download /home/dboles/digital_design/gen_zu_hwsw_vitis/hello/Debug/hello.elf
Info: Cortex-A53 #0 (target 9) Stopped at 0x0 (Cannot resume. Cannot read 'pc'. Cannot read 'r0'. Cortex-A53 #0: EDITR not ready).

I looked through this discussion:
 

and I've validated that I have the preset.xml setting PSU__DDRC__DDR4_ADDR_MAPPING to 0. I have cloned the Digilent fork of the embeddedsw tree, checked out the genesys-zu-22.1 branch, and added it to the Vitis project as suggested. That didn't help. I did a default build of zynqmp_fsb and zynq_pmufw which generated an fsbl.elf and executable.elf in those respective areas. These may not be the right fsbl and pmu trees - I don't know how one would know.

I've seen people talk about creating the platform before the application so I thought I should try that. I created a fresh Vitis project and instead of choosing "Create Application Project" I chose "Create Platform Project". In that wizard it still asks for the XSA file that I'd exported as per the Digilent tutorial. As part of the dialogs there is a place where you can have it build the fsbl and pmu so I de-selected that. After I did that, I continued with creating the platform and added the repository as suggested above. When I then created the application project and built it, I could find an fsbl.elf in the Vitis project area with a matching checksum.

However, I still get the error when I try to "Run As" and run the SW on the board. The bitstream appears to download fine, but I get the write error:

    17:18:24 ERROR : Memory write error at 0x0. Cortex-A53 #0: EDITR not ready

Here is the trace:

vitis_trace.txt

I need to be able to start with a fresh Vivado 2022.2 project and follow the tutorial above.

Thanks

 

Edited May 24, 2023 by mossygreen
I corrected a mistake I had made and got new information

[brvsky]

Same problem here.
I have Genesys ZU 5EV. with kingston DDR
 

The first problem i see the board revision is 'D' on github latest version is 'C'.
https://github.com/Digilent/vivado-boards/tree/master/new/board_files/genesys-zu-5ev/C.0

I  have read:
https://forum.digilent.com/topic/22724-genesys-zu-debugging-error/
https://support.xilinx.com/s/question/0D52E00006pW5zTSAS/error-memory-write-error-at-0x0-cortexa53-0-editr-not-ready-when-trying-to-debug-using-platform-cable-ii?language=en_US
 

But i cannot use it because it is preset for 3EV version. Which use different DDR.
I made changes proposed in AR(from RM).

https://support.xilinx.com/s/article/75768?language=en_US&_ga=2.15018992.798599245.1687769760-485845317.1687513095

List of activities:
1. Just created simple vivado project, applying board preset downloaded by xhub.
2. Removed DP and PCIe ( i'm not interested in using it).
3. Run TCL command for Dynamic DDR.
4. Generate bitstream, any problems.
5. Vitis - create BSP based on XSA file with bitstream.
6. Nothing more added, Clean Project then Build Project  (BSP)
7. Create Application project hello world. Linker script set on DDR ( on OCM code runs )
8.Error while launching program: Memory write error at 0x0. Cortex-A53 #0: EDITR not ready.

I think i've made the possible simplest board test plan.

I'm not used any examples from repo(2020.1 compatibility only). I'm working on Vivado 2023.1 the project will be custom so i need to change hardware and XSA.
Jumper is set on JTAG mode. I tested on SD mode to force JTAG run but error still occurs.

 

 

Edited June 27, 2023 by brvsky
Jumper info