Can't simulate in Vivado, clock is always Z!

[latot]

Hi all!!, I has been able to use Vivado simulation in the past, but now..., I don't have idea why, the clock is always Z in the simulation...

I tried to create a new project, selected:

Board: Arty A100

XDC: https://github.com/Digilent/digilent-xdc/blob/master/Arty-A7-100-Master.xdc

Then in the xdc uncomment:

set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];

set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L24N_T3_35 Sch=led[4]

In a file where I had the blink led example:

`timescale 10ns / 1ns

module blinky(
    input CLK100MHZ,
    output led
    );
    reg[30:0] count = 0;
    assign led = count[10];
    always @ (posedge CLK100MHZ) begin
        count <= count + 1;
        $display("%d", count);
    end
endmodule

 

Then I go to Simulation > Run Simulation, but... the clock will be always on Z, this does not happens before, and I don't get why does not works now..

Thx!

 

[artvvb]

Hi @latot

You should create a testbench for your simulation. This is another Verilog module that will be the top level of the design in the Simulation Sources and will be responsible for generating the clock signal and any other inputs to the design. A basic testbench module for your module might look like the following:

module testbench ();
    reg clk = 0;
    always #1 clk = ~clk;
    wire led;
    blinky dut (
        .CLK100MHZ(clk),
        .led(led)
    );
endmodule

Thanks,

Arthur

[latot]

Mmmm, I try the testbench, well is tricky and is able to simulate the clock, but why the clock does not works now with the blinky example?

[Lloyd Parkes]

3 hours ago, latot said:

 but why the clock does not works now with the blinky example?

Do you have an example where the clock has been simulated in the past? I have only ever seen clocks implemented manually in the testbench code. Maybe in the past you simulated a downloaded project and you didn't notice that it has a testbench in the simulated sources? It would be an easy thing to overlook.

Cheers,
Lloyd

[zygot]

There are some good projects published in various sections of the Digilent Forums with example testbenches for Verilog or VHDL HDL design flow.

[latot]

mm, I think I just get confused, I use to do all tests over the FPGA then I thought... I need to learn to use the simulator, but I didn't expected the clock is not initialized by vivado.

Thx telling me :)

I'm looking on guides and similar to continue learning.

thx!

[zygot]

17 hours ago, latot said:

mm, I think I just get confused

What's confusing you is that Vivado is happy to set your toplevel entity for synthesis as the toplevel entity for simulation and attempt to run a simulation if you tell it to.

So, ask yourself: If I use the code in my toplevel project entity or module for simulation, what exactly am I simulating? 

Let's assume that you have a hardware design that has no input signals. Most programmable devices don't have in internal oscillator or clock source, so such a scenario isn't possible. A few programmable logic devices do have internal clock sources, but for this discussion they aren't relevant. But if you could have a logic design with no input signals, and we ignore external clock inputs, then I suppose that doing a simulation without a testbench entity might be useful. This would be a pretty rare case though, wouldn't you agree?

Vivado does provide example design projects for some of it's IP, like the MIG. In this case, the example project will have a testbench so that you can run a useful simulation. Generally, trying to understand what's going on in these simulations is very difficult, but this is one possible way to learn about how to write a testbench. An easier way would be to see examples of testbench code written to help understand what a design is suppose to do. If you look around you can find these somewhere in the Project Vault or Tutorial sections. You won't become a simulation expert this way, but it is a good way to get started on the learning journey.

Happy hunting!

Edited May 27, 2023 by zygot