ADP5250 Support of Logic Analyzer Clocked or Sync Sampling

[JimR2]

Hi,

Was going through the different ports of my new ADP5250, and was wondering about differences I've noticed between logic analyzer port use on my ADP3450, AD2 and Eclypse board in Waveforms?

One of my favorite use cases is using the logic port to capture ADC data using a synchronization clock input, instead of using a canned sample rate of the device. For this, the "sync" mode has worked very reliably to capture, export and postprocess data in Matlab.

I noticed on my new 5250, however, that the "Mode" pulldown in Waveforms is not active, and appears to always be in "Repeated" mode? So is it correct to assume the other modes available on all other Digilent devices (Shift, Screen, Record and Sync) is not available? If so, is there any way to duplicate the logic sample per sync clock edge behavior (perhaps using the trigger which I had yet to explore).

 

Also, I noticed that the 5250 logic port has a "Clk0" and "Clk1" signal, which is absent on all the other devices, but I can find no documentation on how this is used, nor can I find anywhere in the Waveforms logic setup to make use of it???

Very perplexed, so hopefully there is some insight that can be provided? I bought this device specifically for the 1Gs/s logic capture, but if confined to the pull-down selectable sample rates and not allowed a event driven capture, will be disappointed?

 

Thanks, and look forward to any info that can be shared on this topic.

Regards, JimR2 

 

[attila]

Hi @JimR2

Unfortunately the disabled options are not available with ADP5XXX.

[JimR2]

That is unfortunate, that's been a defining feature of your instruments for me. Is there plans to make them available in the future?

What about the "Clk0" and "Clk1" signal on the logic port? Are these accessible somehow?

I've installed Labview Community Edition, and have been able to access the 5250 via the Waveform VIs (scope and wavegen), but haven't progressed far enough to play with the logic analyzer. Also, is there an updated method to access the 5250 using the Virtualbench VIs? 

I have downloaded Virtualbench from NI (2019) but running standalone it doesn't see the 5250, and the procedure you defined in other posts to copy it from older versions of Labview I can't do, since I can't download an older version of Labview with community edition. Don't want to buy a license for Labviwe if that doesn't provide any additonal ability over Waveforms?

 

Thanks, JimR2

[JimR2]

Just found this comment in the spec's on the 5250 on the Clk0 and Clk1 lines (see attached pic). I missed that before. 

Any info or advice on how they could be accessible via Labview, Virtualbench or Programming would be much appreciated. I've looked around for a VB-8012 manual, but so far have turned up nothing but the specs doc.

 

Thanks, JimR2

 

[attila]

Hi @JimR2

I don't know either the exact purpose of the CLK0/1 lines, except that it could be used as additional digital input channels.
For ADP5250 you could use the LABVIEW VB support. See the following:

 

[JimR2]

That was my first instinct, I had followed the instructions on the link you provided with no luck. So far have not been able to get VB installed in the community version of LabView and working, since you can only download the latest version. Was hoping to figure out what it does before shelling out for a license for LabView.

I was able to install VB and run outside of LabView, but did not recognize the 5250. On the 5250 webpage it says the VB is "unofficially supported", but so far only can assume I need to own a license of LabView, that will give me the ability to download an older version of LabView when VB was supported, then I can follow the procedure in the post. 

Have been getting Waveforms VI's up and running, but doubt that will support them.

Thanks for replying.

[JimR2]

Hi Attila,

I think I've been able to access the clk0/1 pins of the LA on the ADP5250!

I was unable to obtain the VB VI's for the VB8012, so I've been playing with the Digilent provided VI's instead. I noticed when selecting "Description and Tip" on the "Trigger Source" for the "DWF MSO Configure Digital Edge Trigger.vi", that it showed this,

 

With a little playing around, I built a simple LA VI using the Labview Waveforms VI's, and was able to verify that the clk0 on the LA port is accessible this way AND it can provide the behavior similar to the sync mode in Waveforms! To prove this out, I did the following (many pics to follow)......

 I setup my ADP3450 to provide a test stimulus of a walking one's pattern (DIO14:0) to the ADP5250,  and DIO15 I configured as a clock. See pic below.

Then using a simple VI I cobbled together, was able to config the ADP5250, play around with how the VI controls vs what the ADP5250 is actually setting up for some of these (readbacks showed sample rate is always auto adjusted based on data activity, regardless of settings), as well as dump the captured waveform data to a text file viewing.

To see if triggering on DIO15 vs clk0 was any different, The stimulus above I made sure the rising edge of the clock was centered in time with the center of the walking ones' bit.

Then performed two captures, with the PGen/LA wiring as: trigger PGen DIO15 = LA DIO15 , LA clk0=gnd

The captured data below shows a walking one's, but with each being a sequence of 2@ 1's. This appears to be due to the waveform structure or capture itself (maybe you can shed some light here) all events are captured with a time stamp, so the 2@ 1's for each step of the walk is the event when the walking 1 changes to a high state, and the 2nd is when the DIO15 trigger changes to a high state. Thus time stamping at 50us step for a 10KHz walking one, which only changes every 100us.

Then I repeated the capture with the only changes being in the VI below for trigger on clk0, and re-wiring PGen/LA as: trigger PGen DIO15 = LA clk0 , LA DIO15=gnd

This showed a different behavior as seen in the data below, where now only a single bit is captured for each walking one, coincident with the clk0 rising edge!

So this seems to confirm the clk0 isn't really acting as a trigger (maybe my definition is too confining), but more as a what I would call a "sync clock"??

 

So these results seem very promising for me for use on my ADC test-bench to replicate the Waveforms "sync mode", and plan to experiment some more to better understand the flexibility Labview may give over Waveforms. Wanted to pass along in case this information is also useful for others, since finding documentation on the  VB8012 was going nowhere for me. Kind of wish this was specified in the Hardware specs. Kind of glad I missed the mention of the clk0/1 not being supported by Waveforms, may not have purchased the 5250 to begin with? Now I'm hoping to be able to reliably capture higher data-rate up to 32 bits of data!! We'll see.....

 

Regards, JimR2

[attila]

Hi @JimR2

Earlier I've tried using the clk/0-1 with "state mode" but didn't notice any difference.
I don't see the device using the 1MHz clock (dio15->clk0) as sampling clock, applied to clk/0 and setting this as DigitalEdgeTrigger. See the walking1 at 1MHz on the logic input, captured with 1MHz and 2MHz rate.

[JimR2]

Thanks Atilla,

 

So if I understand your post correctly, you've seen no evidence of clk0/1 effective as a trigger in Wafeforms, correct?

I'm a little unclear what you mean by "STATE MODE", can you clarify.

 

I've been playing around a little more with LabView, been a few years since I dabbled with this software tool. I'm more of a Matlab guy, but also have become very fond of the scripting ability in your instruments.

 

I've been poking into the Waveforms VI's to overcome limitations in the "RDWF MSO Read.vi". I realized in the sample size seems to be hadcoded to 16384, and Binary to Waveform conversion VI had compression turned on (see snippet), so the data I showed above may not have been ALL the samples that were occuring. It explains some things, but need to repeat with these limitations overcome, as well as trying to output a BCD value to make sure I know what I'm getting is truly due to the clk0 or clk1.

 

Regards, JimR2

 

[attila]

Hi @JimR2

The clk0-1 works as trigger or digital input but I don't seem to be able to use it as sampling clock. WF/dwf uses the VB CAPI which is similar to the VB VIs.

 

The DWF MSO Read VI allocates 16Ki samples but this can be adjusted:

 

[JimR2]

So I've repeated my measurements now that I have compression turned off, and am seeing what you see, but in LabView. I think having compression turned on, it was only outputting the state changes, and gave me the impression the clk0 was doing something.

I also can configure the trig for dio15, and it behaves accordingly (waits if no trigger present), whereas now when I configure it as mso/clk0, it triggers all the time? Could have sworn I sanity checked that few days ago?

 

Now I'm not so convinced in my finding. Bummer!

 

Jim