Direct JTAG programming with Nexys A7

[Miguel Melendez]

Hello,

I have a project to implement JTAG protocol as defined by ARM debug interface v5 spec.

I have a Nexys A7-100 and noticed that it has direct access to JTAG port pins.

My plan is to use the vivado logic analyzer to debug the JTAG protocol, and my question is

what do you recommend to download to the Nexys A7 to probe JTAG transactions? A JTAG verilog code?

Should I buy the Xilinx USB cable? Can I use your Analog Discovery 2? by the way I have one too. Thanks!

Regards, Miguel

Note: I am colleague of Jalaj. You worked with him on a SWD solution with Analog Discovery 2.

[artvvb]

Some form of JTAG controller is necessary inside the FPGA, if you're trying to implement a controller in verilog, then this would be what you would be debugging. Alternatively, setting up a microblaze debug module with external BSCAN could potentially let you look at JTAG signals. Instantiating a BSCANE2 primitive would be necessary in either case to gain access to the JTAG pins.

Analog Discovery 2 would likely only be helpful insofar as it would be able to decode JTAG transactions, taking the place of the ILA.

Thanks,

Arthur

[Miguel Melendez]

Hello Arthur,

Thank you for the suggestion. I am trying to create a project with Microblaze.

I got stuck with set_property definition for differential clock. How do you set it for Nexys A7?

I have tried:

set_property -dict { PACKAGE_PIN IOSTANDARD DIFF_HSTL E3 } [get_ports {clk_p}];

set_property -dict { PACKAGE_PIN IOSTANDARD DIFF_HSTL D3 } [get_ports {clk_n}];

but it seems to do not be correct. Thanks.

Regards,

Miguel

[artvvb]

The Nexys A7 clock is single-ended, connected only to E3, and a create_clock constraint is required in the XDC file. I'd recommend using the template XDC file or board files - see these guides to install board files and use them with a Microblaze block design: Installing Vivado, Vitis, and Digilent Board Files, Getting Started with Vivado and Vitis for Baremetal Software Projects.

Thanks,

Arthur

 

[Miguel Melendez]

Hi Arthur,

Thank you. I have been able to fix the Clocking Wizard block in Vivado with a single ended clock.

I have created a project using Microblaze IP as shown below in Vivado and able to get the bitstream and xsa files.

and now I am trying to run a C++ program with Vitis. 

All installation seems to be ok and found a GPIO example coming from the drivers, but getting an error and unable to get the makefile:

Thanks in advance for support.

I am very interested to explore the functionality of this Vitis IDE and evaluate the tool's capability for FW development. 

Regards,

Miguel
 

[artvvb]

Hi Miguel,

A makefile error just means the build failed somewhere. There's typically a more informative error message in one of the build consoles, found here:

One thing to check would be for spaces in any folders in the path to the Vitis workspace.

Thanks,

Arthur

[Miguel Melendez]

Hi Arthur,

I have a different question about Nexys A7. Can I use the Xilinx Platform Cable USB II for JTAG communication using J10? Thanks!

Regards,

Miguel