Miguel Melendez

Hello, I am trying to debug a project on Vivado and do not have the JTAG Xilinx Platform USB cable hookup to J10. Is there a workaround? Nexys A7 uses a USB-JTAG circuitry (J6) or should I get a JTAG cable for J10? Thanks. Regards, Miguel

Hi Arthur, I have a different question about Nexys A7. Can I use the Xilinx Platform Cable USB II for JTAG communication using J10? Thanks! Regards, Miguel

Hi Arthur, Thank you. I have been able to fix the Clocking Wizard block in Vivado with a single ended clock. I have created a project using Microblaze IP as shown below in Vivado and able to get the bitstream and xsa files. and now I am trying to run a C++ program with Vitis. All installation seems to be ok and found a GPIO example coming from the drivers, but getting an error and unable to get the makefile: Thanks in advance for support. I am very interested to explore the functionality of this Vitis IDE and evaluate the tool's capability for FW development. Regards, Miguel

Hello Arthur, Thank you for the suggestion. I am trying to create a project with Microblaze. I got stuck with set_property definition for differential clock. How do you set it for Nexys A7? I have tried: set_property -dict { PACKAGE_PIN IOSTANDARD DIFF_HSTL E3 } [get_ports {clk_p}]; set_property -dict { PACKAGE_PIN IOSTANDARD DIFF_HSTL D3 } [get_ports {clk_n}]; but it seems to do not be correct. Thanks. Regards, Miguel

Hello, I have a project to implement JTAG protocol as defined by ARM debug interface v5 spec. I have a Nexys A7-100 and noticed that it has direct access to JTAG port pins. My plan is to use the vivado logic analyzer to debug the JTAG protocol, and my question is what do you recommend to download to the Nexys A7 to probe JTAG transactions? A JTAG verilog code? Should I buy the Xilinx USB cable? Can I use your Analog Discovery 2? by the way I have one too. Thanks! Regards, Miguel Note: I am colleague of Jalaj. You worked with him on a SWD solution with Analog Discovery 2.