zybo z7-20 verilog testbench issue

[mnorth]

Greetings.
I've written a simple verilog LED test for the zybo z7-20 and it works fine.  I wanted to get a testbench going; 
however, inside the testbench module, I cannot seem to generate a clock.  Is it possible that I'm missing
something that ZYNQ's need included?  

[artvvb]

Hi @mnorth

Could you provide more detail about what you're trying to do?

If you're trying to simulate a module written in Verilog, there shouldn't be anything fancy required for Zynq, all stimulus signals including the clock should be generated in the testbench. You'd still just be simulating that Verilog module rather than the whole Zynq system.

If you're trying to clock a design that uses the PL without the Zynq PS, you should likely either 1. use Vitis to run some simple software app, to ensure that the FCLK is running correctly, or 2. use the 125 MHz system clock to clock your design instead of an FCLK, as it is routed directly into PL pins.

Thanks,

Arthur

[mnorth]

sure.  thank you.  I'm using vivado 2021.
I just wanted to see if I could get the zybo to do anything.  I'm a high school teacher just experimenting and mulling things about...
I've reduced my little project down to just this LED aspect. The LED lights fine.
I'm sure I'm doing something very poorly in the testbench given what you've mentioned.
I've reduced my testbench down to what appears to be the generated clock.  

top_module_tb.v

[mnorth]

oh and Arthur...a couple of things:
1.  I did change the 125 MHz clock to 100 MHz
set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { CLK }]; 
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 3.3} [get_ports { CLK }];
2. Eventually, I hope to use PL with the ZYNQ PS component eventually...but, maybe independently at first to avoid extra complexity.
3. I have the free version and can't seem to open Vitis...don't know what that means.

[artvvb]

I don't see anything in particular wrong with the testbench file. Make sure that all of the registers inside the DUT are getting initial values, either in-line with their declaration or in initial statements - uninitialized registers work fine in actual fabric (the actual initial state ought to default to zero), but the simulator can't interpret them and displays value "X" (or "Z").

Quote

1.  I did change the 125 MHz clock to 100 MHz
set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { CLK }]; 
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 3.3} [get_ports { CLK }];

Constraints can't be used to change physical properties of signals, they instead describe what exists on the board - the actual oscillator on the board has a fixed 125 MHz frequency. To get a 100 MHz clock from the 125 MHz system clock, you would typically use clocking hardware in the FPGA like MMCMs/PLLs, which you can instantiate with a Clocking Wizard IP. I'd just start by using the 125 MHz clock directly.

Quote

3. I have the free version and can't seem to open Vitis...don't know what that means.

Vitis is also free. Both it and Vivado get installed if you pick the "Vitis" option in the installer - you likely picked the "Vivado" option, which only installs Vivado. You can rerun the installer by going through Help -> Add Design Tools and Devices in Vivado. That said, skipping Vitis makes perfect sense.