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mnorth

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  1. oh and Arthur...a couple of things: 1. I did change the 125 MHz clock to 100 MHz set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { CLK }]; create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 3.3} [get_ports { CLK }]; 2. Eventually, I hope to use PL with the ZYNQ PS component eventually...but, maybe independently at first to avoid extra complexity. 3. I have the free version and can't seem to open Vitis...don't know what that means.
  2. sure. thank you. I'm using vivado 2021. I just wanted to see if I could get the zybo to do anything. I'm a high school teacher just experimenting and mulling things about... I've reduced my little project down to just this LED aspect. The LED lights fine. I'm sure I'm doing something very poorly in the testbench given what you've mentioned. I've reduced my testbench down to what appears to be the generated clock. top_module_tb.v
  3. Greetings. I've written a simple verilog LED test for the zybo z7-20 and it works fine. I wanted to get a testbench going; however, inside the testbench module, I cannot seem to generate a clock. Is it possible that I'm missing something that ZYNQ's need included?
  4. Hi Atilla. I'd like to discuss how to connect the GPIO of the zyboz7 board to a couple of GPIB-based instruments using a pmod port. Do you have an adapter for that? Maybe what I'm looking for is just a pmod connector to a plan ol' USB?
  5. Sorry, one more question...is the USB JTAG/UART port on the zyboz7 a standard USB to mini-B connector?
  6. HI Atilla. I have your Zyboz7 board. I'd like to figure out how to connect the Arm to a couple of GPIB networkable instruments using a pmod port. Do you sell an adapter for that? I'm guessing it's something like the photo I attached. I have the GPIB‑USB‑HS controller. I'm just making sure...maybe it's just a standard USB out configured with a driver...something like that? I'd also like to fiddle with I2C as an output from a pmod on the zyboz7. Same question...is there any type of special connector to the pmod? thanks!
  7. Got it, but … I think I'm seeing a bit more than this with the various runs I try. The triggering point seems to move with the length of the number of samples. Is there perhaps a way to set the triggering position (left, center, right). It almost seems like the default is center between the front edge and the back edge of the digital signal. I was also looking at the delay wrapper. Could that be useful in any way to this sort of condition? I've been trying to integrate it and haven't seen any effect on the output.
  8. Hi Attila. I'm triggering off the edge of a digital signal generated from DigitalOut. I've generated a triangle wave from AnalogOut and am trying to collect 150 samples from the AnalogIn ADC once the trigger sees the falling edge of the digitalIO. About 50%, of whatever number of samples I use, happens before the falling edge. I'm guessing I'm missing something in the configuration somewhere. Can I set something so that there are relatively no samples taken before the falling edge that the trigger is looking for?
  9. HI Atilla. I'm looking at the dwfconstants.py file and noticed, DwfStateTriggered = c_ubyte(3) DwfStateRunning = c_ubyte(3) Is one of them suppose to be c_ubyte(6) ?
  10. I used your second option. But, it still seems to trigger on the first digitalOut edge and doesn’t appear to recognize any successive. I’ve set up 1000 samples for the 50usec window after the trigger. I get out 1000 samples…and, as expected it's done at that point. No more triggers. More samples just seem to race by the next trigger again. Here’s what I used: AcqHz = c_double(50000000) nSamples = 1000 rgdSamples1 = (c_double*nSamples)() dwf.FDwfAnalogInFrequencySet(hdwf, AcqHz) sRecord = nSamples/AcqHz.value dwf.FDwfAnalogInRecordLengthSet(hdwf, c_double(sRecord)) I would sure appreciate any thoughts you have on this situation. Maybe there’s an example for this situation?
  11. Hi Attila. I've generated a triangle wave and a DigitalOutIO square wave as a test using python. I’d like to take sample(s) from this AnalogIn signal each time the falling-edge of the DigitalOut IO signal occurs throughout a known amount of time for the AnalogIn signal (whatever, ~51msec). Your examples have really helped. Is there an example where a DigitalOut edge is setup as a successive trigger to acquire multiple AnalogIn samples? I’m assuming (?) that this needs a circular buffer.
  12. Thanks Atilla. I'm sending an analog input to Scope 1+. I followed DigitalOut_custom example and in the same trigger code produced a 2usec digitalOut signal with the first 500nsec high, on DIO1. Wanting to write a trigger for the falling edge of this DigitalOut signal and only capture say n samples per falling edge of 100-ish cycles. I'm not sure about the AcqFrqHz ideas...could you give me some ideas about how to choose those numbers? Obviouly, change anything... 100 cycles: c_psecRun = 0.2 sec pattern_repeat = 100 # fixed number nSamples = ??? AcqFrqHz = c_double(???) # SETUP AnalogIn ACQUISITION dwf.FDwfAnalogInChannelEnableSet(hdwf, c_int(0), c_bool(True)) dwf.FDwfAnalogInAcquisitionModeSet(hdwf, acqmodeRecord) dwf.FDwfAnalogInFrequencySet(hdwf, AcqFrqHz) ### RecordLength is in sec. Would record time be the same as c_psecRun ? dwf.FDwfAnalogInRecordLengthSet(hdwf, c_double(nSamples/AcqFrqHz.value)) # SETUP TRIGGER on DOut_1: dwf.FDwfAnalogInTriggerSourceSet(hdwf, trigsrcDetectorDigitalIn) dwf.FDwfDigitalInTriggerSet(hdwf, c_int(0), c_int(0), c_int(0), c_int(1<<1)) ### Is (???), nSamples/pattern_repeat ? dwf.FDwfDigitalInTriggerPositionSet(hdwf, c_int(int( ??? ))) dwf.FDwfDigitalInTriggerCountSet(hdwf, c_int(1), c_int(0)) time.sleep(1) dwf.FDwfAnalogInConfigure(hdwf, c_int(1), c_int(1)) dwf.FDwfDigitalOutConfigure(hdwf, c_int(1))
  13. I may have figured this particular trigger question out ...it appears to be the subtle difference between, trigsrcDetectorDigitalIn and trigsrcDigitalIn.
  14. Thanks Atilla. I am fiddling with a trigger idea using python and have been using example: AnalogIn_Record.py. I'm sending an analog input signal to Scope 1+ and am successfully writing it to the csv file. I followed DigitalOut_custom example and in the same trigger code produced a signal with a period of 2usec with the first 500nsec high, on DIO1. I am hoping to write a trigger for the falling edge of this DigitalOut signal and to only capture say n samples per falling edge. Can we trigger on a digitalOut signal and acquire data from the analogIn? If so, is there an example (I have looked...I could have missed it)? If not, that's interesting...do you have a suggestion?
  15. Thanks Atilla. a few more elementary sounding questions. I wanted to see if I could input something analog trying to use say, AnalogIn_Sample.py... I just connected V+ supply to DIO0 and then 1+...my DMM read ~58mV-ish...the results that printed out weren't good. I looked around for setting the supply power and found: AnalogIO_AnalogDiscovery2_Power.py FDwfAnalogIOChannelNodeSet(hdwf,idxChannel, idxNode, value) # enable positive supply dwf.FDwfAnalogIOChannelNodeSet(hdwf, c_int(0), c_int(0), c_double(True)) # set voltage to 5 V dwf.FDwfAnalogIOChannelNodeSet(hdwf, c_int(0), c_int(1), c_double(5.0)) 1) I don't measure anything out of V+ and nothing from channel 0. 2) I've been reading the API. What exactly is a "Node Index" ? Is that to distinquish between an enable and a set value? 3) So, back to AnalogIn_Sample.py...I don't have a function generator...use an old 10k pot as an input to 1+ ??
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