Compile the VHDL code and download it to the Basys 3 FPGA board

[Esmail]

Hello,

1-  I build a circuit in the SimUAid to count from 0 to 9 by change the inputs as following 

 

2- I removed the 7-segment monitor and named of the output.

3- Convert to VHDL code

4- I open project in vivado and uploaded the VHDL code

5- I need help to remove the error to downloads the code to Basys 3 successfully. 

 

[zygot]

Start fixing errors from the top of you toplevel entity and work you way down.

Your first error is that your VHDL tells synthesis to use a package that, I presume, hasn't been added to the project. Start there.

You've read the documentation for using SimUAid for synthesis, right? Edited May 2, 2023 by zygot

[artvvb]

Hi @Esmail

As zygot mentions, there are modules missing from the project that SimUAid should be providing as a VHDL package, or that might be included somewhere in its installation files. This additional file is necessary to provide the descriptions of the various inverters and logic gates. Digilent unfortunately doesn't have experience with using SimUAid.

Thanks,

Arthur