To Digilent employees: is there any chance to update the tutorial "Arty - Getting Started with Microblaze Servers"?

[zzzhhh]

The tutorial is https://digilent.com/reference/learn/programmable-logic/tutorials/arty-getting-started-with-microblaze-servers/start.

If you follow it, you'll see this tutorial is erroneous under current version of Vivado and Vitis 2022.2.2. So, is there any chance for Digilent to update it so that your customers can follow it without errors? Thanks.

Meanwhile, can you please add a note in red at the beginning of the webpage "This tutorial is erroneous. Please don't follow it in Vivado and Vitis 2022.2.2"? That can at least avoid wasting plenty of time of your customers. Thanks.

 

[artvvb]

On it. No promises on an update, but we'll take a look at it. There are a couple other of these ethernet echo server guides for various boards that could also use some TLC.

Thanks,

Arthur

[zzzhhh]

Thanks for being on it. I can get through the Vivado part. But just can't get through the Vitis part even if I exactly followed the steps. The errors I encountered is 1) DHCP does not work, 2) telnet cannot connect to the server. The error messages I obtained in Vitis Serial Terminal are:

Quote

 

-----lwIP Socket Mode Echo server Demo Application ------
link speed: 100
ERROR: DHCP request timed out
Configuring default IP of 192.168.1.10
Board IP: 192.168.1.10

Netmask : 255.255.255.0

Gateway : 192.168.1.1

              Server   Port Connect With..
-------------------- ------ --------------------
         echo server      7 $ telnet <board_ip> 7

 

Do you have some quick suggestions? I'm using Vivado/Vitis 2022.2.2 on Widows 10.

[zzzhhh]

Seems that this topic was discussed in length long long ago and MicroBlaze + FreeRTOS + lwIP Echo Server on Arty-7 board once worked:

But unfortunately it is not working now. So I continue to ask whether someone, anyone, ever make it under most up-to-date 2022.2.2 version of Vivado/Vitis on Windows 10? Thanks a lot.

Edited April 24, 2023 by zzzhhh

[artvvb]

I need to reproduce the issue to be able to say much. Would you be able to provide your Vivado project?

Not sure if clocks might be the issue, since a baseline link seems to be up (are the LINK/ACT LEDs illuminated?). How are you clocking your design? Is eth_ref_clk still 25 MHz, and what are you using for the Microblaze input clock - an offshoot of the incoming sys_clk, downstream of ui_clk passed through another MMCM, something else?

Switching your board files to a version prior to the switch from v1.0 to v1.1 of the Arty A7 board file could let you follow the design steps for adding the MIG more closely than using 1.1: https://github.com/Digilent/vivado-boards/archive/refs/tags/XilinxBoardStore/v1.zip. That said, you still might run into backbone crit warnings or similar.

Thanks,

Arthur

[dbkincaid]

I wanted to say that I would like to get this demo up as well.  I am looking forward to your update.