I have asked this question over in the xilinx forums already but have not found a solution yet, so I'm reposting it here:
I'm desiging a Zynq-7020 based system where I occasionally need to transfer up to 64MB of data from the PL to the PS. Data is fed into a FIFO before being transmitted via DMA:
s2mm_introut is connected to the Zynq's F2P input. Data is coming into the FIFO at ~1MS/s, the PL is clocked at 100MHz. tlast is asserted on the last sample that is fed into the FIFO:
When the PL tramsits data, Data is received and the ISR is executed, irqStatus reports 0x00005000 (TX Done and DMA Error). Data reception stops after the first block received and subsequent transmissions do not happen at all (data in adcDMAArray are not overwritten and the ISR is not called) - even if i call the dma_init() function again.
S2MM registers:
which, if I interpret it correctly, decodes to:
DMA is running
DMA is halted
DMA internal error
When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.
It seems the error occurs because the amount of data I need to transfer (200kB in this case, but may be up to 64MB) is greater than the maximum of ~128kB (0x3fff 4-byte elements) that was specified in the XAxiDma_SimpleTransfer call (0x3fff is the maximum that can be specified there).
1) Can anybody see what I am doing wrong?
2) if everything worked correctly, how would I know when / if the DMA has finished transmitting all data?
3) Do I need to use the SG engine for large transfers?
Question
connoisseur_de_mimi
Hi,
I have asked this question over in the xilinx forums already but have not found a solution yet, so I'm reposting it here:
I'm desiging a Zynq-7020 based system where I occasionally need to transfer up to 64MB of data from the PL to the PS. Data is fed into a FIFO before being transmitted via DMA:
s2mm_introut is connected to the Zynq's F2P input. Data is coming into the FIFO at ~1MS/s, the PL is clocked at 100MHz. tlast is asserted on the last sample that is fed into the FIFO:
I'm using the https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axidma driver and have set up the DMA in simple mode (init and ISR below):
int dma_init() { XAxiDma_Config *Config = XAxiDma_LookupConfig(XPAR_AXIDMA_0_DEVICE_ID); if (!Config) return XST_FAILURE; if (XAxiDma_CfgInitialize(&dma_, Config) != XST_SUCCESS) return XST_FAILURE; // memset(adcDMAArray, 0, sizeof(adcDMAArray)); Xil_DCacheFlushRange((UINTPTR)adcDMAArray, sizeof(adcDMAArray) / sizeof(adcDMAArray[0])); if (XAxiDma_SimpleTransfer(&dma_, (UINTPTR)adcDMAArray, 0x3fff, XAXIDMA_DEVICE_TO_DMA)) return XST_FAILURE; //disable all interrupts XAxiDma_IntrDisable(&dma_, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DEVICE_TO_DMA); //enable Interrupt On Complete XAxiDma_IntrEnable(&dma_, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DEVICE_TO_DMA); return XST_SUCCESS; }
void dmaDoneCh1IRQHandler(void *callback) { XAxiDma *dma = (XAxiDma *)callback; /* Read pending interrupts */ uint32_t irqStatus = XAxiDma_IntrGetIrq(dma, XAXIDMA_DEVICE_TO_DMA); /* Acknowledge pending interrupts */ XAxiDma_IntrAckIrq(dma, irqStatus, XAXIDMA_DEVICE_TO_DMA); if (irqStatus & XAXIDMA_IRQ_IOC_MASK) { XAxiDma_SimpleTransfer(dma, (UINTPTR)adcDMAArray, 0x3fff, XAXIDMA_DEVICE_TO_DMA); } }
When the PL tramsits data, Data is received and the ISR is executed, irqStatus reports 0x00005000 (TX Done and DMA Error). Data reception stops after the first block received and subsequent transmissions do not happen at all (data in adcDMAArray are not overwritten and the ISR is not called) - even if i call the dma_init() function again.
S2MM registers:
which, if I interpret it correctly, decodes to:
When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.
(from https://docs.xilinx.com/r/en-US/pg021_axi_dma/Stream-to-Memory-Map-Register-Detail)
It seems the error occurs because the amount of data I need to transfer (200kB in this case, but may be up to 64MB) is greater than the maximum of ~128kB (0x3fff 4-byte elements) that was specified in the XAxiDma_SimpleTransfer call (0x3fff is the maximum that can be specified there).
1) Can anybody see what I am doing wrong?
2) if everything worked correctly, how would I know when / if the DMA has finished transmitting all data?
3) Do I need to use the SG engine for large transfers?
Edited by connoisseur_de_mimiLink to comment
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