Bitstream Error

[prudhvi]

sir, 

I am using Xilinx vivado. My project is  Parallel Prefix Adder(PPA).

I have a problem with my project while dumping code.

I have FPGA board of Artix7 it has 4 inputs and 4 outputs

In our project there is 32 bits input and 17 bits output.

My problem is how to dump my project into Artix7 FPGA board

Already try to dump my project but i got a problem while running a Bitstream.

I want a help with process of how to dump 32bit i/p into 4bit Artix7 board.

I just want check my project power, delay, LUTs.

Please help me with this problem

 

Edited April 1, 2023 by prudhvi

[artvvb]

Hi @prudhvi

The error occurs because the block design needs to have an HDL wrapper created for it, and the HDL wrapper needs to be set as the project's top module. The current top module for your project is the apxbt_v1_0 module. I think only constraining the clock port with the ILA as the only output should be sufficient, but in case Vivado optimizes out the majority of your logic in implementation, consider making some of the output ports external (constraining them to a Pmod interface maybe).

Thanks,

Arthur

[prudhvi]

hi @artvvb

Thanks for helping me to complete my project.

👍

 

Edited April 5, 2023 by prudhvi