Genesys ZU3EG - unable run launch application on DDR

[Laerke]

Hello everybody,

I am new to SoC, but was still thinking that "Hello world" would go quite smoothly for me. Not the case. I already spent days on figuring out why I am able to launch only the memory test from the standard template list. More specifically: "Memory Tests" and "Zynq MP DRAM Tests" work and all the rest including "Hello world" don't. I managed to see some activity from an app (see the output of print and xil_printf) only if I switch to OCM.

For my task, I need to enable lpiw, and these examples I can't compile for OCM because they are too big.

Unfortunately, I have no idea on what to do next. Will appreciate if someone could shed some light.

Using Vivado and Vitis 2022.2. Also tried combination Vivado 2022.2 and Vitis 2020.1 with exactly the same result.

XSCT says:

Downloading Program -- /home/workuser/workspace/Hello/Debug/Hello.elf
    section, .text: 0x00000000 - 0x00001513
    section, .init: 0x00001540 - 0x00001573
    section, .fini: 0x00001580 - 0x000015b3
    section, .rodata: 0x000015b8 - 0x00001657
    section, .rodata1: 0x00001658 - 0x0000167f
    section, .sdata2: 0x00001680 - 0x0000167f
    section, .sbss2: 0x00001680 - 0x0000167f
    section, .data: 0x00001680 - 0x00001e37
    section, .data1: 0x00001e38 - 0x00001e3f
    section, .note.gnu.build-id: 0x00001e40 - 0x00001e63
    section, .ctors: 0x00001e64 - 0x00001e7f
    section, .dtors: 0x00001e80 - 0x00001e7f
    section, .eh_frame: 0x00001e80 - 0x00001e83
    section, .mmu_tbl0: 0x00002000 - 0x0000200f
    section, .mmu_tbl1: 0x00003000 - 0x00004fff
    section, .mmu_tbl2: 0x00005000 - 0x00008fff
    section, .preinit_array: 0x00009000 - 0x00008fff
    section, .init_array: 0x00009000 - 0x00009007
    section, .fini_array: 0x00009008 - 0x00009047
    section, .sdata: 0x00009048 - 0x0000907f
    section, .sbss: 0x00009080 - 0x0000907f
    section, .tdata: 0x00009080 - 0x0000907f
    section, .tbss: 0x00009080 - 0x0000907f
    section, .bss: 0x00009080 - 0x000090bf
    section, .heap: 0x000090c0 - 0x0000b0bf
    section, .stack: 0x0000b0c0 - 0x0000e0bf

  0%    0MB   0.0MB/s  ??:?? ETA
100%    0MB   0.2MB/s  00:00    
Setting PC to Program Start Address 0x00000000
Successfully downloaded /home/workuser/workspace/Hello/Debug/Hello.elf
Info: Cortex-A53 #0 (target 9) Running
 

Vitis Serial Terminal:

Release 2022.2   Mar 12 2023  -  08:55:34
PMU-FW is not running, certain applications may not be supported.

Edited March 12, 2023 by Laerke

[JColvin]

Hi @Laerke,

The Zynq Ultrascale chips, such as on the Genesys ZU rely on dynamic DDR initialization that is stored the internal EEPROM (mentioned in the Reference Manual here: https://digilent.com/reference/programmable-logic/genesys-zu/reference-manual#main_memory).

What this means for you, as further explained in this thread: https://forum.digilent.com/topic/24813-setting-up-the-ddr4-on-the-genesys-zu5ev/?sortby=date, is that the Xilinx FSBL code only compiles for Xilinx dev boards. To run the Genesys ZU as well, you need to add the patch made by Digilent (linked in the forum thread in the previous sentence). In terms of the Hello World specifically, Digilent has a release that already includes the needed patch in this guide here: https://digilent.com/reference/programmable-logic/genesys-zu/demos/hello-world.

Let me know if you have any questions.

Thanks,
JColvin

 

[Laerke]

Hi @JColvin,

Thank you very much for your feedback and the provided links. With the precompiled fsbl, I managed to successfully run the examples on DDR using Vitis 2022.2.

However, when looking at the https://github.com/Digilent/embeddedsw repository, it appears to me that only ZCU102 is supported?

 

Edited March 14, 2023 by Laerke

[JColvin]

Hi @Laerke,

I believe you'll be needing a specific branch of that repository, https://github.com/Digilent/embeddedsw/tree/genesys-zu-22.1; it doesn't specifically call out the Genesys ZU 3EG or 5EV, but I think this might just be that the readme wasn't specifically updated from the Xilinx variant? I've reached out to somebody more familiar with the Genesys ZU material to get some clarification on this.

Thanks,
JColvin

[Laerke]

Hi @JColvin,

I walked through these repositories, but no luck. So would be nice to hear more on that, then. Thanks for help!

[BogdanVanca]

Hi @Laerke,

From what I remember the precompiled FSBL contains this fix:  https://github.com/Digilent/embeddedsw/commit/6e9e2fa973f2c27d3f979f3c07afdbe616f694a4

Xilinx promised to include this fix in their latest release. If you have any questions or other problems with this board, please tag me in your thread.