[Help] Time, execution and sincronization of circuits in FPGA

[latot]

Hi all!, Here again with more weird questions :)

 

From the start, FPGA is presented to be able to create "circuits" in a dynamic way (verilog, vhdl, any language we wants), it is great, is just that when I was testing I realizes in the guides, I wasn't able to find a good description of how the timing works.

In my basic and maybe inaccurate explanation, there is some things the I would to know better.

Clock: All the FPGA have a clock, and the clock have two stages, posedge and negedge.

Circuits: Th circuits that are used by the FPGA.

Is difficult to me talks about this, because if I talk about one thing that confuses me, it will open a new one too so...

The clock, the we know i has a frequency, but... when it will apply the circuits? because for example, the FPGA will mode from posedge to negedge, to do this, all the new circuits must run on the actual values of the memory/wires, but if one value changes, that would cause some values to be updated with wrong values (the new ones). Obvs, the actual FPGA probably already have a way to solve this, so what is the question? well when we simulate a circuit in vivado, the change from posedge and nedgedge is... instantaneous.... that is what I don't get, in the middle of it there should be this system that handle part of the FPGA integrity. Maybe the simulations does not show it, and there it is...

I feel like someone will tell me, check this link about how FPGA works.. xD

Oks now... circuits!... how to handle circuits, we build circuits, they must be reminded, the question would be how the circuits are handled.

Lets pick as example, "wire" signal, a wire must be connected all the time!, yes or yes, some circuits are sensitive, but how is handled in a consistent way? how are the circuits keep consistent in all the work?

I read some of this is not perfect, we can check that in:

https://verilogguide.readthedocs.io/en/latest/verilog/procedure.html#guidelines-for-using-always-block

There is some cases where we get weird things working with the clock, and assignments...

Even after all this, is possible that there is no a general answer to this, because every problem maybe would be fixed in differents FPGA...

If everything works like the theory says, probs the second part of this questions would not exists :)

Thx!