How to add Gaussian noise/any other noise to sine wave(using VHDL)?

[Anwesa Roy]

We need a noisy sine wave signal. We have generated the sine wave(using VHDL), but we cant figure out how to add noise to it. We are including the code for sine wave generation. Kindly mention how to add Gaussian/any other noise to it.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;  --try to use this library as much as possible.

entity sine_wave is
port (clk :in  std_logic;
      data_out : out STD_LOGIC_VECTOR(7 downto 0)
      );
end sine_wave;

architecture Behavioral of sine_wave is
signal i : integer range 0 to 29:=0;
--type memory_type is array (0 to 29) of integer;
type memory_type is array (0 to 29) of std_logic_vector(7 downto 0); 
--ROM for storing the sine values generated by MATLAB.
signal sine : memory_type :=("01001101","01011101","01101100","01111010","10000111","10010000","10010111","10011010","10011010","10010111","10010000","10000111","01111010","01101100","01011101","01001101",
"00111101","00101110","00100000","00010011","00001010","00000011","00000000","00000000","00000011","00001010","00010011","00100000","00101110","00111101");
--hi
begin

process(clk)
begin
  --to check the rising edge of the clock signal
if(rising_edge(clk)) then     
data_out <= sine(i);
i <= i+ 1;
if(i = 29) then
i <= 0;
end if;
end if;
end process;

end Behavioral;

 

[D@n]

Try using an LRS.  You should be able to look them up on line.  Taps and fill will be specific to your application, but a Verilog example might look like:

assign w_nxtbit= r_fill[0]^r_fill[15]^r_fill[1];
always @(posedge i_clk)
  r_fill <= { r_fill[(NTAPS-2):0], w_nxtbit };

To get more Gaussian, ,as opposed to this binary, noise--just add many of these together.

Dan

[D@n]

Here's a better discussion of LFSR's (Linear Feedback Shift Registers), and doing so from within VHDL.  Add N of these together and you should have something with a variance of N/4, and a mean of N/2.

Dan