I've been using the Digital Discovery to dump time interleaved ADC data captured in FPGA RAM, each at 60MSPS (for an interleaved data rate of 120MSPS).
In Synchronous capture mode, the Rate: is only representative of the data time sequence step, which when dumped from RAM could be any rate! In this case 120MSPS.
When I set the Rate: setting to 120MHz to get the timescale in the log data correct for FFT analysis, it defaults back to 100MHz.
Of course I can correct this on the post-processing end, but was wondering if this default could be over-ridden? Or at the very least considered for a future version update, if only for the Sync case where the 100MHz limit really doesn't apply?
Question
JimR2
Hi,
I've been using the Digital Discovery to dump time interleaved ADC data captured in FPGA RAM, each at 60MSPS (for an interleaved data rate of 120MSPS).
In Synchronous capture mode, the Rate: is only representative of the data time sequence step, which when dumped from RAM could be any rate! In this case 120MSPS.
When I set the Rate: setting to 120MHz to get the timescale in the log data correct for FFT analysis, it defaults back to 100MHz.
Of course I can correct this on the post-processing end, but was wondering if this default could be over-ridden? Or at the very least considered for a future version update, if only for the Sync case where the 100MHz limit really doesn't apply?
Thanks, JimR2
Link to comment
Share on other sites
3 answers to this question
Recommended Posts
Create an account or sign in to comment
You need to be a member in order to leave a comment
Create an account
Sign up for a new account in our community. It's easy!
Register a new accountSign in
Already have an account? Sign in here.
Sign In Now