Setting Up the DDR4 on the Genesys ZU5EV

[vz49]

Hi there, 

I have a difficult time setting up the HyperX HX424S14IB/4 DDR4 ram on my Genesys zu5EV board.

 

What I have tried:

1. using the 5EV board presets without any changes.

2. Enabling Dynamic DDR Configuration in Vivado

3. Try to setup the values inside the DDR controller windows inside the MPSOC IP. Unfortunately, the amount of info i can get from the manufacture datasheet is very limited. Link: https://www.kingston.com/dataSheets/HX424S14IB_4.pdf

 

So far I have no success running a simply "hello world" baremetal application on ddr.

Obivously, I tweak the Linker Script to run my code on OCM only. Everything is working perfectly without ddr.

I am pretty sure that, the DDR controller is not setup/ Intitalized correctly to communicate with the HyperX HX424S14IB/4, therefore loading the code on to ddr is impossible and leads to error:

"Error while launching program: 
Memory write error at 0x0. Cortex-A53 #0: EDITR not ready"

I did some reading on this forum that it is something to do with the FSBL, and this issue is not 100% solved even to this day. Let me know if I am wrong. I wish someone can jump in and give me some guidence.

I am using Vivado 2022.1 and Vitis 2022.1

 

Thanks

Vincent

 

Edited January 30, 2023 by vz49

[elodg]

As explained in the RM, the DDR4 modules require dynamic DDR init, which is enabled in Vivado (sets a config parameter), and performed by the FSBL. The Xilinx FSBL code has conditional compiles only for Xilinx dev boards and our patches add the Genesys ZU too. You  may use the pre-compiled FSBL from https://github.com/Digilent/Genesys-ZU/releases/tag/5EV%2FHELLO-WORLD%2F2022.1-2 with your own application. Or you can add the following repo to your Vitis workspace: https://github.com/Digilent/embeddedsw/tree/genesys-zu-22.1. This latter has the patches applied to the FSBL and will pull those in whenever you generate an FSBL project.

[vz49]

@elodg Hi, thanks for the feedback. I have just tested the Hello World Example on my 5EV, it works beautifully.

You mentioned that the dynamic DDR initialization only works on xilinx "approved" developement board, including the the Genesys.

Does it mean that all custom zynq mpsoc board cannot access this feature?

If that is the case, it is better to setup the DDR4 config directly inside Vivado.

Forgive me I am a novice, I simply has no clue how to setup the HyperX Ram supplied on the 5EV. It seems the datasheet is not providing full info of how the ram should be setup. 

It would be great if digilent can provide a solid setting of the HyperX Ram inside Vivado DDR setup, therefore users does not have to fiddle with the FSBL DDR Initialization hassle unless they choose to upgrade to different model. 

Let me know if I am optimalistic or wrong. Once again, thanks for the headup. Cheers.

[elodg]

The dynamic init feature is only enabled on Xilinx dev kits in the Xilinx FSBL. It can be easily enabled for other boards by patching the FSBL sources.

The HyperX DIMM shipped with the G-ZU *should* work with the preset and static init. We will look into why this is not the case.

[vz49]

@elodgI am happy to report that using the "custom genesys zu5ev repo" inside vitis has been great and smooth. The DDR4 HyperX is initialized and run successfully using the 5ev board preset inside Vivado.

I typed "set_property CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN 1 [get_bd_cells /zynq_ultra_ps_e_0]" in the tcl console to make sure the te dynamic ddr config feature is on.

Thanks for the help. Appreicate it!

Best,

Vincent