qdewolf Posted January 14, 2023 Share Posted January 14, 2023 the spec for the ADP5250 says 3.3v logic out" 5 V compatible TTL input / 3.3 V LVTTL output" . since there is no support for the pattern generator how is the digital out meant to be controlled? Link to comment Share on other sites More sharing options...
1 JColvin Posted January 14, 2023 Share Posted January 14, 2023 Hi @qdewolf, The digital out pins would instead be controlled through the Static I/O tool. It is definitely more limited in functionality than a pattern generator (since that was not available with the NI Virtual Bench 8012, which is the underlying hardware of the ADP5250), but at least is not nothing. Let me know if you have any questions. Thanks, JColvin Link to comment Share on other sites More sharing options...
0 qdewolf Posted January 14, 2023 Author Share Posted January 14, 2023 could you script this with enough performance to send a packet on an i2c bus? Link to comment Share on other sites More sharing options...
0 attila Posted January 16, 2023 Share Posted January 16, 2023 Hi @qdewolf The next sw version will support I2C master for ADP5250. I hope to have it ready this week. bryan78 and qdewolf 2 Link to comment Share on other sites More sharing options...
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qdewolf
the spec for the ADP5250 says 3.3v logic out"
5 V compatible TTL input / 3.3 V LVTTL output"
. since there is no support for the pattern generator how is the digital out meant to be controlled?
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