A0-A5 Pins not working

[robb]

Hello

I am using the Arty Z7-10 board. I am very new to hardware development and am going through the demos Diligent offers. I wish to use the Single ended ADC pins (A0-A5), however I have not been able to get them working. 

I used the XADC demo for the differential pins (1st link below) as a guide for implementing the single ended pins, but even with reconfiguring the XADC (see 1st figure) nothing happens. I left the .v file alone, but even the switches wont even turn on the LEDs like it did for the original demo.

I did read the manual and I have all the updated files, I just don't know how to do this. Any material and helps appreciated.

Thank you

Used this demo (works): https://digilent.com/reference/programmable-logic/arty-z7/demos/xadc?redirect=1

 

[JColvin]

Hi @robb,

I unfortunately did not get the opportunity to adjust the HDL and .xdc to the pins you wish to use, but the problem you are running into is that the silkscreen pin number of the analog input pins is not necessarily the same as the XADC channel number in the Zynq processor in the Arty Z7 itself.

Based on page 9 of the schematic on Bank 35, https://files.digilent.com/resources/programmable-logic/arty-z7/arty-z7-d0-sch.PDF, the chipkit A0 through A5 (correspondingly named CK_AN<X>_P) are associated with the following channel numbers on the channel sequencer (which you can tell based on the "_AD#P" portion of the actual pin name on the Zynq chip).

CK_AN0 = vauxp1
CK_AN1 = vauxp9
CK_AN2 = vauxp6
CK_AN3 = vauxp15
CK_AN4 = vauxp5
CK_AN5 = vauxp13

After enabling those channels, the .xdc would need to be adjusted to correctly enable those pins (a master .xdc listing all of the pins is available here https://github.com/Digilent/digilent-xdc/blob/master/Arty-Z7-10-Master.xdc)

As for why this isn't better detailed or explained in the reference manual or the demo page is a great question; I have put in a request to get this corrected, though with the Thanksgiving week here in the US I do not anticipating this happening until at least next week. I should be able to help you further with this project then as well.

Please let me know if you have any questions.

Thanks,
JColvin

[robb]

Hope you had a good Thanksgiving @JColvin

 

I did know about the xdc files for my board and the schematic for the single ended adc pins. I used the correct pins according to the schematic and manual. 

I will attach my code and my constraint file.

XADCdemo.v Arty-Z7-10-Master.xdc

[artvvb]

Hi @robb

XADCdemo.v also needs to be modified in order to access other XADC channels. The lines setting the value of the Address_in register ("Address_in <= 8'h1C;") and using the channel_out signal ("channel_out == 8'h1C") hardcode XADC DRP register addresses that correspond to the XADC results registers. The demo as posted only reads from channels 12 (address 0x1C) and 0 (address 0x10). See Xilinx UG480 for more info on the register space of the DRP interface.

Thanks,

Arthur