Having a little trouble compiling...

[Nevermnd]

Hey all,

So I wasn't quite sure if I should ask this on the Vivado forum, or here...

However, I do have two Digilent Boards, the Basys 3 and Nexus 4 DDR.

I've basically been trying to 'self teach' myself FPGA via a textbook: Digital System Design with FPGA Implementation

But I've been struggling a bit with the 'compiling/implementation' step.

Grant I am using Vivado 2018.2 (I know there are obviously much more recent versions, but the install is *huge*-- I mean 225-250 GB?!? You *must be kidding me*),

And this should be just enough for my simple purposes.

In any case,

#1 I realized I had to manually install the board packages, which I think I have done successfully.

#2 Even though the related IP is explicitly stated in the code, I realized I have to manually add the IP to the project-- Having done so now it will run simulation, even synthesis:

But when I get to the last step, implementation, it is 'bugging out' and I'm really not sure what is wrong.

The code itself is two files, so a bit long to directly include here, but as stated, does come from a textbook, so I hope that's 'not wrong'. It is a simple VGA display 'test application'

I think I may have just not configured the IP right when I added it, but I didn't think that should be 'something you have to think about', if you already 'call it up in the code'.

In any case, any help would be appreciated, as like I said I am 'learning this on my own', so I have no 'professor' to ask about it.

And, even, the response it provides about the VCC clock not being connected is fairly clear... But I am still like 'what?'

Best,

-A

 

Edited November 8, 2022 by Nevermnd

[JColvin]

Hi @Nevermnd,

I'm not able to directly tell from your screenshots, but are you using a .xdc file to tell Vivado where pins are located, such as clk_pin1?

I personally haven't used the book you referenced, but Digilent has a small guide on creating hardware only designs here, https://digilent.com/reference/programmable-logic/guides/getting-started-with-vivado, which should hopefully address some of the compiling problems you mentioned.

In terms of reference projects, the OOB (out of box) demo for the Nexys A7 (what the Nexys 4 DDR was rebranded to) https://digilent.com/reference/programmable-logic/nexys-a7/start#example_projects, and the General I/O demo for the Basys 3 https://digilent.com/reference/programmable-logic/basys-3/start#example_projects, both use the VGA ports so you can have a working HDL project to compare to.

Let me know if you have any questions.

Thanks,
JColvin

P.S. Regarding the large Vivado installation size -- it should not be that large. I'm not sure how easy it is uninstall parts you do not need for Xilinx software, but during the installation process you only need to have the Artix-7 box checked under the 7-Series dropdown if you are using the Basys 3 and Nexys A7 (reference picture below is showing what I have checked that covers all of the Digilent boards)

I'd also recommend checking the file format for wherever you happen to be installing the Xilinx software; for example, Xilinx software stored on an exFAT file system takes up way more disk space than it does on a NFTS system.